From b731550236e531552a5855bf32af644316cb9fe4 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 18 Jan 2024 10:52:37 -0700 Subject: soc/amd/*: Rename Makefiles from .inc to .mk The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth Change-Id: Ie449267fe4fdd75110f577e1b9f748cd06140950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80071 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Felix Singer --- src/soc/amd/cezanne/Makefile.inc | 257 --------------- src/soc/amd/cezanne/Makefile.mk | 257 +++++++++++++++ src/soc/amd/cezanne/psp_verstage/Makefile.inc | 14 - src/soc/amd/cezanne/psp_verstage/Makefile.mk | 14 + src/soc/amd/common/Makefile.inc | 94 ------ src/soc/amd/common/Makefile.mk | 94 ++++++ src/soc/amd/common/block/Makefile.inc | 8 - src/soc/amd/common/block/Makefile.mk | 8 + src/soc/amd/common/block/acp/Makefile.inc | 6 - src/soc/amd/common/block/acp/Makefile.mk | 6 + src/soc/amd/common/block/acpi/Makefile.inc | 21 -- src/soc/amd/common/block/acpi/Makefile.mk | 21 ++ src/soc/amd/common/block/acpimmio/Makefile.inc | 15 - src/soc/amd/common/block/acpimmio/Makefile.mk | 15 + src/soc/amd/common/block/alink/Makefile.inc | 7 - src/soc/amd/common/block/alink/Makefile.mk | 7 + src/soc/amd/common/block/aoac/Makefile.inc | 9 - src/soc/amd/common/block/aoac/Makefile.mk | 9 + src/soc/amd/common/block/apob/Makefile.inc | 6 - src/soc/amd/common/block/apob/Makefile.mk | 6 + src/soc/amd/common/block/cpu/Makefile.inc | 26 -- src/soc/amd/common/block/cpu/Makefile.mk | 26 ++ src/soc/amd/common/block/cpu/car/Makefile.inc | 13 - src/soc/amd/common/block/cpu/car/Makefile.mk | 13 + src/soc/amd/common/block/cpu/mca/Makefile.inc | 15 - src/soc/amd/common/block/cpu/mca/Makefile.mk | 15 + src/soc/amd/common/block/cpu/noncar/Makefile.inc | 17 - src/soc/amd/common/block/cpu/noncar/Makefile.mk | 17 + src/soc/amd/common/block/cpu/smm/Makefile.inc | 12 - src/soc/amd/common/block/cpu/smm/Makefile.mk | 12 + src/soc/amd/common/block/cpu/tsc/Makefile.inc | 11 - src/soc/amd/common/block/cpu/tsc/Makefile.mk | 11 + src/soc/amd/common/block/data_fabric/Makefile.inc | 17 - src/soc/amd/common/block/data_fabric/Makefile.mk | 17 + src/soc/amd/common/block/emmc/Makefile.inc | 2 - src/soc/amd/common/block/emmc/Makefile.mk | 2 + src/soc/amd/common/block/gpio/Makefile.inc | 11 - src/soc/amd/common/block/gpio/Makefile.mk | 11 + src/soc/amd/common/block/graphics/Makefile.inc | 2 - src/soc/amd/common/block/graphics/Makefile.mk | 2 + src/soc/amd/common/block/hda/Makefile.inc | 2 - src/soc/amd/common/block/hda/Makefile.mk | 2 + src/soc/amd/common/block/i2c/Makefile.inc | 4 - src/soc/amd/common/block/i2c/Makefile.mk | 4 + src/soc/amd/common/block/iommu/Makefile.inc | 2 - src/soc/amd/common/block/iommu/Makefile.mk | 2 + src/soc/amd/common/block/lpc/Makefile.inc | 16 - src/soc/amd/common/block/lpc/Makefile.mk | 16 + src/soc/amd/common/block/pci/Makefile.inc | 15 - src/soc/amd/common/block/pci/Makefile.mk | 15 + src/soc/amd/common/block/pm/Makefile.inc | 9 - src/soc/amd/common/block/pm/Makefile.mk | 9 + src/soc/amd/common/block/psp/Makefile.inc | 34 -- src/soc/amd/common/block/psp/Makefile.mk | 34 ++ src/soc/amd/common/block/root_complex/Makefile.inc | 2 - src/soc/amd/common/block/root_complex/Makefile.mk | 2 + src/soc/amd/common/block/sata/Makefile.inc | 2 - src/soc/amd/common/block/sata/Makefile.mk | 2 + src/soc/amd/common/block/simnow/Makefile.inc | 7 - src/soc/amd/common/block/simnow/Makefile.mk | 7 + src/soc/amd/common/block/smbus/Makefile.inc | 9 - src/soc/amd/common/block/smbus/Makefile.mk | 9 + src/soc/amd/common/block/smi/Makefile.inc | 9 - src/soc/amd/common/block/smi/Makefile.mk | 9 + src/soc/amd/common/block/smn/Makefile.inc | 9 - src/soc/amd/common/block/smn/Makefile.mk | 9 + src/soc/amd/common/block/smu/Makefile.inc | 7 - src/soc/amd/common/block/smu/Makefile.mk | 7 + src/soc/amd/common/block/spi/Makefile.inc | 25 -- src/soc/amd/common/block/spi/Makefile.mk | 25 ++ src/soc/amd/common/block/stb/Makefile.inc | 8 - src/soc/amd/common/block/stb/Makefile.mk | 8 + src/soc/amd/common/block/uart/Makefile.inc | 13 - src/soc/amd/common/block/uart/Makefile.mk | 13 + src/soc/amd/common/block/xhci/Makefile.inc | 4 - src/soc/amd/common/block/xhci/Makefile.mk | 4 + src/soc/amd/common/fsp/Makefile.inc | 28 -- src/soc/amd/common/fsp/Makefile.mk | 28 ++ src/soc/amd/common/fsp/pci/Makefile.inc | 5 - src/soc/amd/common/fsp/pci/Makefile.mk | 5 + src/soc/amd/common/pi/Makefile.inc | 23 -- src/soc/amd/common/pi/Makefile.mk | 23 ++ src/soc/amd/common/psp_verstage/Makefile.inc | 34 -- src/soc/amd/common/psp_verstage/Makefile.mk | 34 ++ src/soc/amd/common/vboot/Makefile.inc | 20 -- src/soc/amd/common/vboot/Makefile.mk | 20 ++ src/soc/amd/genoa_poc/Makefile.inc | 151 --------- src/soc/amd/genoa_poc/Makefile.mk | 151 +++++++++ src/soc/amd/glinda/Makefile.inc | 292 ---------------- src/soc/amd/glinda/Makefile.mk | 292 ++++++++++++++++ src/soc/amd/glinda/psp_verstage/Makefile.inc | 19 -- src/soc/amd/glinda/psp_verstage/Makefile.mk | 19 ++ src/soc/amd/mendocino/Makefile.inc | 366 --------------------- src/soc/amd/mendocino/Makefile.mk | 366 +++++++++++++++++++++ src/soc/amd/mendocino/psp_verstage/Makefile.inc | 14 - src/soc/amd/mendocino/psp_verstage/Makefile.mk | 14 + src/soc/amd/phoenix/Makefile.inc | 357 -------------------- src/soc/amd/phoenix/Makefile.mk | 357 ++++++++++++++++++++ src/soc/amd/phoenix/psp_verstage/Makefile.inc | 14 - src/soc/amd/phoenix/psp_verstage/Makefile.mk | 14 + src/soc/amd/picasso/Makefile.inc | 271 --------------- src/soc/amd/picasso/Makefile.mk | 271 +++++++++++++++ src/soc/amd/picasso/psp_verstage/Makefile.inc | 10 - src/soc/amd/picasso/psp_verstage/Makefile.mk | 10 + src/soc/amd/stoneyridge/Makefile.inc | 192 ----------- src/soc/amd/stoneyridge/Makefile.mk | 192 +++++++++++ 106 files changed, 2536 insertions(+), 2536 deletions(-) delete mode 100644 src/soc/amd/cezanne/Makefile.inc create mode 100644 src/soc/amd/cezanne/Makefile.mk delete mode 100644 src/soc/amd/cezanne/psp_verstage/Makefile.inc create mode 100644 src/soc/amd/cezanne/psp_verstage/Makefile.mk delete mode 100644 src/soc/amd/common/Makefile.inc create mode 100644 src/soc/amd/common/Makefile.mk delete mode 100644 src/soc/amd/common/block/Makefile.inc create mode 100644 src/soc/amd/common/block/Makefile.mk delete mode 100644 src/soc/amd/common/block/acp/Makefile.inc create mode 100644 src/soc/amd/common/block/acp/Makefile.mk delete mode 100644 src/soc/amd/common/block/acpi/Makefile.inc create mode 100644 src/soc/amd/common/block/acpi/Makefile.mk delete mode 100644 src/soc/amd/common/block/acpimmio/Makefile.inc create mode 100644 src/soc/amd/common/block/acpimmio/Makefile.mk delete mode 100644 src/soc/amd/common/block/alink/Makefile.inc create mode 100644 src/soc/amd/common/block/alink/Makefile.mk delete mode 100644 src/soc/amd/common/block/aoac/Makefile.inc create mode 100644 src/soc/amd/common/block/aoac/Makefile.mk delete mode 100644 src/soc/amd/common/block/apob/Makefile.inc create mode 100644 src/soc/amd/common/block/apob/Makefile.mk delete mode 100644 src/soc/amd/common/block/cpu/Makefile.inc create mode 100644 src/soc/amd/common/block/cpu/Makefile.mk delete mode 100644 src/soc/amd/common/block/cpu/car/Makefile.inc create mode 100644 src/soc/amd/common/block/cpu/car/Makefile.mk delete mode 100644 src/soc/amd/common/block/cpu/mca/Makefile.inc create mode 100644 src/soc/amd/common/block/cpu/mca/Makefile.mk delete mode 100644 src/soc/amd/common/block/cpu/noncar/Makefile.inc create mode 100644 src/soc/amd/common/block/cpu/noncar/Makefile.mk delete mode 100644 src/soc/amd/common/block/cpu/smm/Makefile.inc create mode 100644 src/soc/amd/common/block/cpu/smm/Makefile.mk delete mode 100644 src/soc/amd/common/block/cpu/tsc/Makefile.inc create mode 100644 src/soc/amd/common/block/cpu/tsc/Makefile.mk delete mode 100644 src/soc/amd/common/block/data_fabric/Makefile.inc create mode 100644 src/soc/amd/common/block/data_fabric/Makefile.mk delete mode 100644 src/soc/amd/common/block/emmc/Makefile.inc create mode 100644 src/soc/amd/common/block/emmc/Makefile.mk delete mode 100644 src/soc/amd/common/block/gpio/Makefile.inc create mode 100644 src/soc/amd/common/block/gpio/Makefile.mk delete mode 100644 src/soc/amd/common/block/graphics/Makefile.inc create mode 100644 src/soc/amd/common/block/graphics/Makefile.mk delete mode 100644 src/soc/amd/common/block/hda/Makefile.inc create mode 100644 src/soc/amd/common/block/hda/Makefile.mk delete mode 100644 src/soc/amd/common/block/i2c/Makefile.inc create mode 100644 src/soc/amd/common/block/i2c/Makefile.mk delete mode 100644 src/soc/amd/common/block/iommu/Makefile.inc create mode 100644 src/soc/amd/common/block/iommu/Makefile.mk delete mode 100644 src/soc/amd/common/block/lpc/Makefile.inc create mode 100644 src/soc/amd/common/block/lpc/Makefile.mk delete mode 100644 src/soc/amd/common/block/pci/Makefile.inc create mode 100644 src/soc/amd/common/block/pci/Makefile.mk delete mode 100644 src/soc/amd/common/block/pm/Makefile.inc create mode 100644 src/soc/amd/common/block/pm/Makefile.mk delete mode 100644 src/soc/amd/common/block/psp/Makefile.inc create mode 100644 src/soc/amd/common/block/psp/Makefile.mk delete mode 100644 src/soc/amd/common/block/root_complex/Makefile.inc create mode 100644 src/soc/amd/common/block/root_complex/Makefile.mk delete mode 100644 src/soc/amd/common/block/sata/Makefile.inc create mode 100644 src/soc/amd/common/block/sata/Makefile.mk delete mode 100644 src/soc/amd/common/block/simnow/Makefile.inc create mode 100644 src/soc/amd/common/block/simnow/Makefile.mk delete mode 100644 src/soc/amd/common/block/smbus/Makefile.inc create mode 100644 src/soc/amd/common/block/smbus/Makefile.mk delete mode 100644 src/soc/amd/common/block/smi/Makefile.inc create mode 100644 src/soc/amd/common/block/smi/Makefile.mk delete mode 100644 src/soc/amd/common/block/smn/Makefile.inc create mode 100644 src/soc/amd/common/block/smn/Makefile.mk delete mode 100644 src/soc/amd/common/block/smu/Makefile.inc create mode 100644 src/soc/amd/common/block/smu/Makefile.mk delete mode 100644 src/soc/amd/common/block/spi/Makefile.inc create mode 100644 src/soc/amd/common/block/spi/Makefile.mk delete mode 100644 src/soc/amd/common/block/stb/Makefile.inc create mode 100644 src/soc/amd/common/block/stb/Makefile.mk delete mode 100644 src/soc/amd/common/block/uart/Makefile.inc create mode 100644 src/soc/amd/common/block/uart/Makefile.mk delete mode 100644 src/soc/amd/common/block/xhci/Makefile.inc create mode 100644 src/soc/amd/common/block/xhci/Makefile.mk delete mode 100644 src/soc/amd/common/fsp/Makefile.inc create mode 100644 src/soc/amd/common/fsp/Makefile.mk delete mode 100644 src/soc/amd/common/fsp/pci/Makefile.inc create mode 100644 src/soc/amd/common/fsp/pci/Makefile.mk delete mode 100644 src/soc/amd/common/pi/Makefile.inc create mode 100644 src/soc/amd/common/pi/Makefile.mk delete mode 100644 src/soc/amd/common/psp_verstage/Makefile.inc create mode 100644 src/soc/amd/common/psp_verstage/Makefile.mk delete mode 100644 src/soc/amd/common/vboot/Makefile.inc create mode 100644 src/soc/amd/common/vboot/Makefile.mk delete mode 100644 src/soc/amd/genoa_poc/Makefile.inc create mode 100644 src/soc/amd/genoa_poc/Makefile.mk delete mode 100644 src/soc/amd/glinda/Makefile.inc create mode 100644 src/soc/amd/glinda/Makefile.mk delete mode 100644 src/soc/amd/glinda/psp_verstage/Makefile.inc create mode 100644 src/soc/amd/glinda/psp_verstage/Makefile.mk delete mode 100644 src/soc/amd/mendocino/Makefile.inc create mode 100644 src/soc/amd/mendocino/Makefile.mk delete mode 100644 src/soc/amd/mendocino/psp_verstage/Makefile.inc create mode 100644 src/soc/amd/mendocino/psp_verstage/Makefile.mk delete mode 100644 src/soc/amd/phoenix/Makefile.inc create mode 100644 src/soc/amd/phoenix/Makefile.mk delete mode 100644 src/soc/amd/phoenix/psp_verstage/Makefile.inc create mode 100644 src/soc/amd/phoenix/psp_verstage/Makefile.mk delete mode 100644 src/soc/amd/picasso/Makefile.inc create mode 100644 src/soc/amd/picasso/Makefile.mk delete mode 100644 src/soc/amd/picasso/psp_verstage/Makefile.inc create mode 100644 src/soc/amd/picasso/psp_verstage/Makefile.mk delete mode 100644 src/soc/amd/stoneyridge/Makefile.inc create mode 100644 src/soc/amd/stoneyridge/Makefile.mk (limited to 'src/soc') diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc deleted file mode 100644 index dedf98c4bd..0000000000 --- a/src/soc/amd/cezanne/Makefile.inc +++ /dev/null @@ -1,257 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) - -subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage - -# Beware that all-y also adds the compilation unit to verstage on PSP -all-y += aoac.c -all-y += config.c -all-y += i2c.c - -# all_x86-y adds the compilation unit to all stages that run on the x86 cores -all_x86-y += gpio.c -all_x86-y += uart.c - -bootblock-y += early_fch.c -bootblock-y += espi_util.c - -romstage-y += fsp_m_params.c - -ramstage-y += acpi.c -ramstage-y += agesa_acpi.c -ramstage-y += chip.c -ramstage-y += cpu.c -ramstage-y += fch.c -ramstage-y += fsp_s_params.c -ramstage-y += graphics.c -ramstage-y += mca.c -ramstage-y += root_complex.c -ramstage-y += xhci.c - -smm-y += gpio.c -smm-y += smihandler.c -smm-$(CONFIG_DEBUG_SMI) += uart.c - -CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include -CPPFLAGS_common += -I$(src)/soc/amd/cezanne/acpi -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common - -# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes -# Building the cbfs image will fail if the offset isn't large enough -AMD_FW_AB_POSITION := 0x40 - -CEZANNE_FW_A_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) - -CEZANNE_FW_B_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) -# -# PSP Directory Table items -# -# Certain ordering requirements apply, however these are ensured by amdfwtool. -# For more information see "AMD Platform Security Processor BIOS Architecture -# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). -# - - -ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) -PSP_SOFTFUSE_BITS += 7 -endif - -ifeq ($(CONFIG_PSP_INIT_ESPI),y) -PSP_SOFTFUSE_BITS += 15 -endif - -ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) -# Enable secure debug unlock -PSP_SOFTFUSE_BITS += 0 -OPT_TOKEN_UNLOCK="--token-unlock" -endif - -ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) -OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" -else -# Disable MP2 firmware loading -PSP_SOFTFUSE_BITS += 29 -endif - -ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) -PSP_SOFTFUSE_BITS += 58 -endif - -# Use additional Soft Fuse bits specified in Kconfig -PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) - -# type = 0x3a -ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) -PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) -endif - -# type = 0x55 -SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) - -# -# BIOS Directory Table items - proper ordering is managed by amdfwtool -# - -# type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) - -# type = 0x61 -PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) - -# type = 0x62 -PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img -PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') - -ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) -# type = 0x63 - construct APOB NV base/size from flash map -# The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) -APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) -endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# type = 0x6B - PSP Shared memory location -ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) -PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) -PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) -endif - -# type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) -PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) -endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK - -# Helper function to return a value with given bit set -# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. -set-bit=$(call int-shift-left, 1 $(call _toint,$1)) -PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) - -# -# Build the arguments to amdfwtool (order is unimportant). Missing file names -# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. -# - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) -OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) - -OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ - $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ - $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) - -OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) -OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) -OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) -OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) - -OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) -OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) -OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) -OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) -OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) -OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) -OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) - -OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) - -OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) -OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) - -AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ - $(OPT_APOB_ADDR) \ - $(OPT_DEBUG_AMDFWTOOL) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_LOAD_MP2_FW) \ - --use-pspsecureos \ - --load-s0i3 \ - $(OPT_TOKEN_UNLOCK) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_SPL_TABLE_FILE) \ - $(OPT_PSP_SHAREDMEM_BASE) \ - $(OPT_PSP_SHAREDMEM_SIZE) \ - $(OPT_EFS_SPI_READ_MODE) \ - $(OPT_EFS_SPI_SPEED) \ - $(OPT_EFS_SPI_MICRON_FLAG) \ - --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --flashsize $(CONFIG_ROM_SIZE) - -$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ - $(PSP_VERSTAGE_FILE) \ - $(PSP_VERSTAGE_SIG_FILE) \ - $$(PSP_APCB_FILES) \ - $(DEP_FILES) \ - $(AMDFWTOOL) \ - $(obj)/fmap_config.h \ - $(objcbfs)/bootblock.elf # this target also creates the .map file - $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - $(OPT_VERSTAGE_FILE) \ - $(OPT_VERSTAGE_SIG_FILE) \ - --location $(CONFIG_AMD_FWM_POSITION) \ - --multilevel \ - --output $@ - -$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) - rm -f $@ - @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) - -$(obj)/amdfw_a.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - --location $(call _tohex,$(CEZANNE_FW_A_POSITION)) \ - --anywhere \ - --multilevel \ - --output $@ - -$(obj)/amdfw_b.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - --location $(call _tohex,$(CEZANNE_FW_B_POSITION)) \ - --anywhere \ - --multilevel \ - --output $@ - - -ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -cbfs-files-y += apu/amdfw_a -apu/amdfw_a-file := $(obj)/amdfw_a.rom -# Ensure this ends up at the beginning of the FW_MAIN_A fmap region -apu/amdfw_a-position := $(AMD_FW_AB_POSITION) -apu/amdfw_a-type := raw -endif - -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -cbfs-files-y += apu/amdfw_b -apu/amdfw_b-file := $(obj)/amdfw_b.rom -# Ensure this ends up at the beginning of the FW_MAIN_B fmap region -apu/amdfw_b-position := $(AMD_FW_AB_POSITION) -apu/amdfw_b-type := raw -endif - -endif # ($(CONFIG_SOC_AMD_CEZANNE),y) diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk new file mode 100644 index 0000000000..dedf98c4bd --- /dev/null +++ b/src/soc/amd/cezanne/Makefile.mk @@ -0,0 +1,257 @@ +# SPDX-License-Identifier: BSD-3-Clause + +ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) + +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage + +# Beware that all-y also adds the compilation unit to verstage on PSP +all-y += aoac.c +all-y += config.c +all-y += i2c.c + +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + +bootblock-y += early_fch.c +bootblock-y += espi_util.c + +romstage-y += fsp_m_params.c + +ramstage-y += acpi.c +ramstage-y += agesa_acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += fch.c +ramstage-y += fsp_s_params.c +ramstage-y += graphics.c +ramstage-y += mca.c +ramstage-y += root_complex.c +ramstage-y += xhci.c + +smm-y += gpio.c +smm-y += smihandler.c +smm-$(CONFIG_DEBUG_SMI) += uart.c + +CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include +CPPFLAGS_common += -I$(src)/soc/amd/cezanne/acpi +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common + +# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes +# Building the cbfs image will fail if the offset isn't large enough +AMD_FW_AB_POSITION := 0x40 + +CEZANNE_FW_A_POSITION=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) + +CEZANNE_FW_B_POSITION=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Architecture +# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). +# + + +ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) +PSP_SOFTFUSE_BITS += 7 +endif + +ifeq ($(CONFIG_PSP_INIT_ESPI),y) +PSP_SOFTFUSE_BITS += 15 +endif + +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" +endif + +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" +else +# Disable MP2 firmware loading +PSP_SOFTFUSE_BITS += 29 +endif + +ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) +PSP_SOFTFUSE_BITS += 58 +endif + +# Use additional Soft Fuse bits specified in Kconfig +PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif + +# type = 0x55 +SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') + +ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) +# type = 0x63 - construct APOB NV base/size from flash map +# The flashmap section used for this is expected to be named RW_MRC_CACHE +APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) +endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +# type = 0x6B - PSP Shared memory location +ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) +PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) +PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) +endif + +# type = 0x52 - PSP Bootloader Userspace Application (verstage) +PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) +PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) +endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK + +# Helper function to return a value with given bit set +# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) +OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) + +OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ + $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ + $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) +OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) +OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) +OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) + +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + $(OPT_DEBUG_AMDFWTOOL) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + $(OPT_PSP_LOAD_MP2_FW) \ + --use-pspsecureos \ + --load-s0i3 \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_SPL_TABLE_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --flashsize $(CONFIG_ROM_SIZE) + +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $(PSP_VERSTAGE_FILE) \ + $(PSP_VERSTAGE_SIG_FILE) \ + $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ + $(AMDFWTOOL) \ + $(obj)/fmap_config.h \ + $(objcbfs)/bootblock.elf # this target also creates the .map file + $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ + --location $(CONFIG_AMD_FWM_POSITION) \ + --multilevel \ + --output $@ + +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + +$(obj)/amdfw_a.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + --location $(call _tohex,$(CEZANNE_FW_A_POSITION)) \ + --anywhere \ + --multilevel \ + --output $@ + +$(obj)/amdfw_b.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + --location $(call _tohex,$(CEZANNE_FW_B_POSITION)) \ + --anywhere \ + --multilevel \ + --output $@ + + +ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_a +apu/amdfw_a-file := $(obj)/amdfw_a.rom +# Ensure this ends up at the beginning of the FW_MAIN_A fmap region +apu/amdfw_a-position := $(AMD_FW_AB_POSITION) +apu/amdfw_a-type := raw +endif + +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_b +apu/amdfw_b-file := $(obj)/amdfw_b.rom +# Ensure this ends up at the beginning of the FW_MAIN_B fmap region +apu/amdfw_b-position := $(AMD_FW_AB_POSITION) +apu/amdfw_b-type := raw +endif + +endif # ($(CONFIG_SOC_AMD_CEZANNE),y) diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.inc b/src/soc/amd/cezanne/psp_verstage/Makefile.inc deleted file mode 100644 index 2cb1345365..0000000000 --- a/src/soc/amd/cezanne/psp_verstage/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/cezanne/include - -verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include - -subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage - -verstage-y += svc.c -verstage-y += chipset.c -verstage-y += uart.c - -verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S -verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.mk b/src/soc/amd/cezanne/psp_verstage/Makefile.mk new file mode 100644 index 0000000000..2cb1345365 --- /dev/null +++ b/src/soc/amd/cezanne/psp_verstage/Makefile.mk @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/cezanne/include + +verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include + +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage + +verstage-y += svc.c +verstage-y += chipset.c +verstage-y += uart.c + +verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc deleted file mode 100644 index 626260f93e..0000000000 --- a/src/soc/amd/common/Makefile.inc +++ /dev/null @@ -1,94 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON),y) -subdirs-y += block -subdirs-y += fsp -subdirs-y += pi -subdirs-y += vboot - -CPPFLAGS_common += -I$(src)/soc/amd/common/vboot/include - -ifneq ($(V),) -OPT_DEBUG_AMDFWTOOL = --debug -endif - -ifneq ($(CONFIG_AMDFW_CONFIG_FILE), ) -FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') - -# Add all the files listed in the config file to the dependency list -POUND_SIGN=$(call strip_quotes, "\#") -REMOVE_MP2 = -# If the MP2 file is not being loaded, remove it as a dependency -ifneq ($(CONFIG_PSP_LOAD_MP2_FW),y) -REMOVE_MP2 = /MP2/d -endif - -# Steps below to generate the dependency list -# 1a: Delete any line that starts with #, FIRMWARE_LOCATION, SOC_NAME, or AMD_FUSE_CHAIN -# 1b: Filter out lines containing MP2 or not, decided above. -# 1c: Use awk to return only field 2, the filename -# 2: Gather filenames with no path to add the firmware location later -# 3: Gather filenames with a path -# 4a: Add the firmware location to any files without a path to the dependencies -# 4b: add the lines containing a path to the dependencies -AMDFW_CFG_FILES = $(shell sed "/^$(POUND_SIGN)\|^FIRMWARE_LOCATION\|^AMD_FUSE_CHAIN\|^SOC_NAME/d; \ - $(REMOVE_MP2)" $(CONFIG_AMDFW_CONFIG_FILE) | \ - awk '{print $$2}') -AMDFW_CFG_IN_FW_LOC = $(shell echo "$(AMDFW_CFG_FILES)" | tr ' ' '\n' | grep -v "/") -AMDFW_CFG_WITH_PATH = $(shell echo "$(AMDFW_CFG_FILES)" | tr ' ' '\n' | grep "/") -DEP_FILES = $(patsubst %,$(FIRMWARE_LOCATION)/%, $(AMDFW_CFG_IN_FW_LOC)) \ - $(AMDFW_CFG_WITH_PATH) - -amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*U?odePatch*.bin) - -ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) -$(objcbfs)/bootblock.bin: $(obj)/amdfw.rom $(obj)/fmap_config.h - cp $< $@ - -amdfw_region_start=$(subst $(spc),,FMAP_SECTION_$(call regions-for-file,apu/amdfw)_START) -amdfw_offset=$(call int-subtract, \ - $(CONFIG_AMD_FWM_POSITION) \ - $(call int-subtract, \ - $(call get_fmap_value,$(amdfw_region_start)) \ - $(call get_fmap_value,FMAP_SECTION_FLASH_START))) - -add_bootblock = \ - $(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \ - -b $(amdfw_offset) -r $(call regions-for-file,apu/amdfw) \ - $(CBFSTOOL_ADD_CMD_OPTIONS) - -endif # ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) - -ifeq ($(CONFIG_VBOOT_GSCVD),y) -build_complete:: $(obj)/ro-amdfw-list - -$(obj)/ro-amdfw-list: $(AMDFWREAD) - $(AMDFWREAD) --ro-list $(obj)/coreboot.rom > $@ - -amdfwread-offset-size-cmd = grep '$(1)' $(obj)/ro-amdfw-list | \ - sed 's/^.* 0x0*\(.*\) 0x0*\(.*\)$$/\1:\2/' - -amdfwread-range-cmd = $(shell ( \ - range=$$($(call amdfwread-offset-size-cmd,$(1))) ;\ - if [ -n "$$range" ]; then \ - printf $$range ;\ - else \ - printf "error" ;\ - fi ;\ -)) -endif # ifeq ($(CONFIG_VBOOT_GSCVD),y) - -endif # ifneq ($(CONFIG_AMDFW_CONFIG_FILE), ) - -MAINBOARD_BLOBS_DIR := $(call strip_quotes, $(CONFIG_APCB_BLOBS_DIR)) - -PHONY+=warn_no_apcb -warn_no_apcb: - printf "\n\t** WARNING **\n" - printf "coreboot has been built without an APCB.\n" - printf "This image will not boot.\n\n" - -PHONY+=die_no_apcb -die_no_apcb: warn_no_apcb - $(error This board requires the APCB to build correctly) - -endif # ifeq ($(CONFIG_SOC_AMD_COMMON),y) diff --git a/src/soc/amd/common/Makefile.mk b/src/soc/amd/common/Makefile.mk new file mode 100644 index 0000000000..626260f93e --- /dev/null +++ b/src/soc/amd/common/Makefile.mk @@ -0,0 +1,94 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON),y) +subdirs-y += block +subdirs-y += fsp +subdirs-y += pi +subdirs-y += vboot + +CPPFLAGS_common += -I$(src)/soc/amd/common/vboot/include + +ifneq ($(V),) +OPT_DEBUG_AMDFWTOOL = --debug +endif + +ifneq ($(CONFIG_AMDFW_CONFIG_FILE), ) +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') + +# Add all the files listed in the config file to the dependency list +POUND_SIGN=$(call strip_quotes, "\#") +REMOVE_MP2 = +# If the MP2 file is not being loaded, remove it as a dependency +ifneq ($(CONFIG_PSP_LOAD_MP2_FW),y) +REMOVE_MP2 = /MP2/d +endif + +# Steps below to generate the dependency list +# 1a: Delete any line that starts with #, FIRMWARE_LOCATION, SOC_NAME, or AMD_FUSE_CHAIN +# 1b: Filter out lines containing MP2 or not, decided above. +# 1c: Use awk to return only field 2, the filename +# 2: Gather filenames with no path to add the firmware location later +# 3: Gather filenames with a path +# 4a: Add the firmware location to any files without a path to the dependencies +# 4b: add the lines containing a path to the dependencies +AMDFW_CFG_FILES = $(shell sed "/^$(POUND_SIGN)\|^FIRMWARE_LOCATION\|^AMD_FUSE_CHAIN\|^SOC_NAME/d; \ + $(REMOVE_MP2)" $(CONFIG_AMDFW_CONFIG_FILE) | \ + awk '{print $$2}') +AMDFW_CFG_IN_FW_LOC = $(shell echo "$(AMDFW_CFG_FILES)" | tr ' ' '\n' | grep -v "/") +AMDFW_CFG_WITH_PATH = $(shell echo "$(AMDFW_CFG_FILES)" | tr ' ' '\n' | grep "/") +DEP_FILES = $(patsubst %,$(FIRMWARE_LOCATION)/%, $(AMDFW_CFG_IN_FW_LOC)) \ + $(AMDFW_CFG_WITH_PATH) + +amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*U?odePatch*.bin) + +ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) +$(objcbfs)/bootblock.bin: $(obj)/amdfw.rom $(obj)/fmap_config.h + cp $< $@ + +amdfw_region_start=$(subst $(spc),,FMAP_SECTION_$(call regions-for-file,apu/amdfw)_START) +amdfw_offset=$(call int-subtract, \ + $(CONFIG_AMD_FWM_POSITION) \ + $(call int-subtract, \ + $(call get_fmap_value,$(amdfw_region_start)) \ + $(call get_fmap_value,FMAP_SECTION_FLASH_START))) + +add_bootblock = \ + $(CBFSTOOL) $(1) add -f $(2) -n apu/amdfw -t amdfw \ + -b $(amdfw_offset) -r $(call regions-for-file,apu/amdfw) \ + $(CBFSTOOL_ADD_CMD_OPTIONS) + +endif # ifeq ($(CONFIG_RESET_VECTOR_IN_RAM),y) + +ifeq ($(CONFIG_VBOOT_GSCVD),y) +build_complete:: $(obj)/ro-amdfw-list + +$(obj)/ro-amdfw-list: $(AMDFWREAD) + $(AMDFWREAD) --ro-list $(obj)/coreboot.rom > $@ + +amdfwread-offset-size-cmd = grep '$(1)' $(obj)/ro-amdfw-list | \ + sed 's/^.* 0x0*\(.*\) 0x0*\(.*\)$$/\1:\2/' + +amdfwread-range-cmd = $(shell ( \ + range=$$($(call amdfwread-offset-size-cmd,$(1))) ;\ + if [ -n "$$range" ]; then \ + printf $$range ;\ + else \ + printf "error" ;\ + fi ;\ +)) +endif # ifeq ($(CONFIG_VBOOT_GSCVD),y) + +endif # ifneq ($(CONFIG_AMDFW_CONFIG_FILE), ) + +MAINBOARD_BLOBS_DIR := $(call strip_quotes, $(CONFIG_APCB_BLOBS_DIR)) + +PHONY+=warn_no_apcb +warn_no_apcb: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without an APCB.\n" + printf "This image will not boot.\n\n" + +PHONY+=die_no_apcb +die_no_apcb: warn_no_apcb + $(error This board requires the APCB to build correctly) + +endif # ifeq ($(CONFIG_SOC_AMD_COMMON),y) diff --git a/src/soc/amd/common/block/Makefile.inc b/src/soc/amd/common/block/Makefile.inc deleted file mode 100644 index eeebadf2b2..0000000000 --- a/src/soc/amd/common/block/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON),y) - -subdirs-y += ./* - -CPPFLAGS_common += -I$(src)/soc/amd/common/block/include/ - -endif diff --git a/src/soc/amd/common/block/Makefile.mk b/src/soc/amd/common/block/Makefile.mk new file mode 100644 index 0000000000..eeebadf2b2 --- /dev/null +++ b/src/soc/amd/common/block/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON),y) + +subdirs-y += ./* + +CPPFLAGS_common += -I$(src)/soc/amd/common/block/include/ + +endif diff --git a/src/soc/amd/common/block/acp/Makefile.inc b/src/soc/amd/common/block/acp/Makefile.inc deleted file mode 100644 index 343e3a703f..0000000000 --- a/src/soc/amd/common/block/acp/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp_gen1.c - -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN2) += acp.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN2) += acp_gen2.c diff --git a/src/soc/amd/common/block/acp/Makefile.mk b/src/soc/amd/common/block/acp/Makefile.mk new file mode 100644 index 0000000000..343e3a703f --- /dev/null +++ b/src/soc/amd/common/block/acp/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp_gen1.c + +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN2) += acp.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN2) += acp_gen2.c diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc deleted file mode 100644 index 763a3bc61a..0000000000 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI),y) - -all_x86-y += acpi.c -smm-y += acpi.c - -ramstage-y += pm_state.c -ramstage-y += tables.c -ramstage-$(CONFIG_ACPI_BERT) += bert.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_ALIB) += alib.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_CPPC) += cppc.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE) += cpu_power_state.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_GPIO) += gpio.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_IVRS) += ivrs.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_MADT) += madt.c - -romstage-y += elog.c -ramstage-y += elog.c -smm-y += elog.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPI diff --git a/src/soc/amd/common/block/acpi/Makefile.mk b/src/soc/amd/common/block/acpi/Makefile.mk new file mode 100644 index 0000000000..763a3bc61a --- /dev/null +++ b/src/soc/amd/common/block/acpi/Makefile.mk @@ -0,0 +1,21 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI),y) + +all_x86-y += acpi.c +smm-y += acpi.c + +ramstage-y += pm_state.c +ramstage-y += tables.c +ramstage-$(CONFIG_ACPI_BERT) += bert.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_ALIB) += alib.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_CPPC) += cppc.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE) += cpu_power_state.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_GPIO) += gpio.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_IVRS) += ivrs.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_MADT) += madt.c + +romstage-y += elog.c +ramstage-y += elog.c +smm-y += elog.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPI diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc deleted file mode 100644 index 269117358e..0000000000 --- a/src/soc/amd/common/block/acpimmio/Makefile.inc +++ /dev/null @@ -1,15 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO),y) - -all-y += mmio_util.c -smm-y += mmio_util.c - -all-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS) += pm_io_access_util.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS) += pm_io_access_util.c - -all-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM) += biosram.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM) += biosram.c - -bootblock-y += print_reset_status.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO diff --git a/src/soc/amd/common/block/acpimmio/Makefile.mk b/src/soc/amd/common/block/acpimmio/Makefile.mk new file mode 100644 index 0000000000..269117358e --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/Makefile.mk @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO),y) + +all-y += mmio_util.c +smm-y += mmio_util.c + +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS) += pm_io_access_util.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS) += pm_io_access_util.c + +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM) += biosram.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM) += biosram.c + +bootblock-y += print_reset_status.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO diff --git a/src/soc/amd/common/block/alink/Makefile.inc b/src/soc/amd/common/block/alink/Makefile.inc deleted file mode 100644 index ef0728afc8..0000000000 --- a/src/soc/amd/common/block/alink/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK),y) - -all_x86-y += alink.c -smm-y += alink.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_ALINK diff --git a/src/soc/amd/common/block/alink/Makefile.mk b/src/soc/amd/common/block/alink/Makefile.mk new file mode 100644 index 0000000000..ef0728afc8 --- /dev/null +++ b/src/soc/amd/common/block/alink/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK),y) + +all_x86-y += alink.c +smm-y += alink.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_ALINK diff --git a/src/soc/amd/common/block/aoac/Makefile.inc b/src/soc/amd/common/block/aoac/Makefile.inc deleted file mode 100644 index 21f0727134..0000000000 --- a/src/soc/amd/common/block/aoac/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_AOAC),y) - -bootblock-y += aoac.c -romstage-y += aoac.c -verstage-y += aoac.c -ramstage-y += aoac.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_AOAC diff --git a/src/soc/amd/common/block/aoac/Makefile.mk b/src/soc/amd/common/block/aoac/Makefile.mk new file mode 100644 index 0000000000..21f0727134 --- /dev/null +++ b/src/soc/amd/common/block/aoac/Makefile.mk @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_AOAC),y) + +bootblock-y += aoac.c +romstage-y += aoac.c +verstage-y += aoac.c +ramstage-y += aoac.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_AOAC diff --git a/src/soc/amd/common/block/apob/Makefile.inc b/src/soc/amd/common/block/apob/Makefile.inc deleted file mode 100644 index d7e27a2d14..0000000000 --- a/src/soc/amd/common/block/apob/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_APOB) += apob_cache.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_APOB) += apob_cache.c - -endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE diff --git a/src/soc/amd/common/block/apob/Makefile.mk b/src/soc/amd/common/block/apob/Makefile.mk new file mode 100644 index 0000000000..d7e27a2d14 --- /dev/null +++ b/src/soc/amd/common/block/apob/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_APOB) += apob_cache.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_APOB) += apob_cache.c + +endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc deleted file mode 100644 index 1c4331cb91..0000000000 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ /dev/null @@ -1,26 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -subdirs-y += ./* - -romstage-y += cpu.c - -ramstage-y += cpu.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SVI2) += svi2.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SVI3) += svi3.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE) += update_microcode.c - -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE),y) -define add-ucode-as-cbfs -$(if $(value cpu_microcode_$(2).bin-file),$(info File1: $(cpu_microcode_$(2).bin-file)) $(info File2: $(1)) $(error Error: The cbfs filename "cpu_microcode_$(2).bin" is used for both above files. Check your microcode patches for duplicates.)) -cbfs-files-y += cpu_microcode_$(2).bin -cpu_microcode_$(2).bin-file := $(1) -cpu_microcode_$(2).bin-type := microcode - -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) -cpu_microcode_$(2).bin-align := 64 -else -cpu_microcode_$(2).bin-align := 16 -endif -endef - -$(foreach ucode,$(amd_microcode_bins),$(eval $(call add-ucode-as-cbfs,$(ucode),$(shell hexdump -n 2 -s 0x18 -e '"%x"' $(ucode))))) -endif diff --git a/src/soc/amd/common/block/cpu/Makefile.mk b/src/soc/amd/common/block/cpu/Makefile.mk new file mode 100644 index 0000000000..1c4331cb91 --- /dev/null +++ b/src/soc/amd/common/block/cpu/Makefile.mk @@ -0,0 +1,26 @@ +## SPDX-License-Identifier: GPL-2.0-only +subdirs-y += ./* + +romstage-y += cpu.c + +ramstage-y += cpu.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SVI2) += svi2.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SVI3) += svi3.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE) += update_microcode.c + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE),y) +define add-ucode-as-cbfs +$(if $(value cpu_microcode_$(2).bin-file),$(info File1: $(cpu_microcode_$(2).bin-file)) $(info File2: $(1)) $(error Error: The cbfs filename "cpu_microcode_$(2).bin" is used for both above files. Check your microcode patches for duplicates.)) +cbfs-files-y += cpu_microcode_$(2).bin +cpu_microcode_$(2).bin-file := $(1) +cpu_microcode_$(2).bin-type := microcode + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +cpu_microcode_$(2).bin-align := 64 +else +cpu_microcode_$(2).bin-align := 16 +endif +endef + +$(foreach ucode,$(amd_microcode_bins),$(eval $(call add-ucode-as-cbfs,$(ucode),$(shell hexdump -n 2 -s 0x18 -e '"%x"' $(ucode))))) +endif diff --git a/src/soc/amd/common/block/cpu/car/Makefile.inc b/src/soc/amd/common/block/cpu/car/Makefile.inc deleted file mode 100644 index 5116c56cd1..0000000000 --- a/src/soc/amd/common/block/cpu/car/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_CAR),y) - -bootblock-y += cache_as_ram.S -bootblock-y += ap_exit_car.S -bootblock-y += exit_car.S - -postcar-y += exit_car.S - -romstage-y += ap_exit_car.S -romstage-y += exit_car.S - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_CAR diff --git a/src/soc/amd/common/block/cpu/car/Makefile.mk b/src/soc/amd/common/block/cpu/car/Makefile.mk new file mode 100644 index 0000000000..5116c56cd1 --- /dev/null +++ b/src/soc/amd/common/block/cpu/car/Makefile.mk @@ -0,0 +1,13 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_CAR),y) + +bootblock-y += cache_as_ram.S +bootblock-y += ap_exit_car.S +bootblock-y += exit_car.S + +postcar-y += exit_car.S + +romstage-y += ap_exit_car.S +romstage-y += exit_car.S + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_CAR diff --git a/src/soc/amd/common/block/cpu/mca/Makefile.inc b/src/soc/amd/common/block/cpu/mca/Makefile.inc deleted file mode 100644 index c8120be97e..0000000000 --- a/src/soc/amd/common/block/cpu/mca/Makefile.inc +++ /dev/null @@ -1,15 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_MCA_COMMON),y) -ramstage-y += mca_common.c -ramstage-$(CONFIG_ACPI_BERT) += mca_common_bert.c -endif # CONFIG_SOC_AMD_COMMON_BLOCK_MCA_COMMON - -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_MCA),y) -ramstage-$(CONFIG_ACPI_BERT) += mca_bert.c -ramstage-y += mca.c -endif # CONFIG_SOC_AMD_COMMON_BLOCK_MCA - -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_MCAX),y) -ramstage-$(CONFIG_ACPI_BERT) += mcax_bert.c -ramstage-y += mcax.c -endif # CONFIG_SOC_AMD_COMMON_BLOCK_MCAX diff --git a/src/soc/amd/common/block/cpu/mca/Makefile.mk b/src/soc/amd/common/block/cpu/mca/Makefile.mk new file mode 100644 index 0000000000..c8120be97e --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/Makefile.mk @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_MCA_COMMON),y) +ramstage-y += mca_common.c +ramstage-$(CONFIG_ACPI_BERT) += mca_common_bert.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_MCA_COMMON + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_MCA),y) +ramstage-$(CONFIG_ACPI_BERT) += mca_bert.c +ramstage-y += mca.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_MCA + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_MCAX),y) +ramstage-$(CONFIG_ACPI_BERT) += mcax_bert.c +ramstage-y += mcax.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_MCAX diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc deleted file mode 100644 index f3ada6250f..0000000000 --- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y) - -bootblock-y += bootblock.c -bootblock-y += cpu.c -bootblock-y += early_cache.c -bootblock-y += pre_c.S -bootblock-y += write_resume_eip.c -bootblock-$(CONFIG_TPM_MEASURED_BOOT) += bootblock_measure.c -romstage-y += memmap.c -romstage-y += romstage.c -ramstage-y += cpu.c -romstage-y += cpu.c -ramstage-y += memmap.c -ramstage-y += mpinit.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.mk b/src/soc/amd/common/block/cpu/noncar/Makefile.mk new file mode 100644 index 0000000000..f3ada6250f --- /dev/null +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.mk @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y) + +bootblock-y += bootblock.c +bootblock-y += cpu.c +bootblock-y += early_cache.c +bootblock-y += pre_c.S +bootblock-y += write_resume_eip.c +bootblock-$(CONFIG_TPM_MEASURED_BOOT) += bootblock_measure.c +romstage-y += memmap.c +romstage-y += romstage.c +ramstage-y += cpu.c +romstage-y += cpu.c +ramstage-y += memmap.c +ramstage-y += mpinit.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/common/block/cpu/smm/Makefile.inc b/src/soc/amd/common/block/cpu/smm/Makefile.inc deleted file mode 100644 index 9562d43f2d..0000000000 --- a/src/soc/amd/common/block/cpu/smm/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMM),y) - -romstage-y += smm_helper.c -postcar-y += smm_helper.c -ramstage-y += finalize.c -ramstage-y += smm_relocate.c -ramstage-y += smm_helper.c -smm-y += smi_apmc.c -smm-y += smi_handler.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/common/block/cpu/smm/Makefile.mk b/src/soc/amd/common/block/cpu/smm/Makefile.mk new file mode 100644 index 0000000000..9562d43f2d --- /dev/null +++ b/src/soc/amd/common/block/cpu/smm/Makefile.mk @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMM),y) + +romstage-y += smm_helper.c +postcar-y += smm_helper.c +ramstage-y += finalize.c +ramstage-y += smm_relocate.c +ramstage-y += smm_helper.c +smm-y += smi_apmc.c +smm-y += smi_handler.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/common/block/cpu/tsc/Makefile.inc b/src/soc/amd/common/block/cpu/tsc/Makefile.inc deleted file mode 100644 index 4ec0e0fa52..0000000000 --- a/src/soc/amd/common/block/cpu/tsc/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c -all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c -all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c -all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c - -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c diff --git a/src/soc/amd/common/block/cpu/tsc/Makefile.mk b/src/soc/amd/common/block/cpu/tsc/Makefile.mk new file mode 100644 index 0000000000..4ec0e0fa52 --- /dev/null +++ b/src/soc/amd/common/block/cpu/tsc/Makefile.mk @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c + +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c diff --git a/src/soc/amd/common/block/data_fabric/Makefile.inc b/src/soc/amd/common/block/data_fabric/Makefile.inc deleted file mode 100644 index b0684f4e75..0000000000 --- a/src/soc/amd/common/block/data_fabric/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC) += data_fabric_helper.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += domain.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION) += np_region.c - -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT),y) -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += pci_segment_multi.c -else -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += pci_segment_single.c -endif - -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO),y) -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += extended_mmio.c -else -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += mmio.c -endif diff --git a/src/soc/amd/common/block/data_fabric/Makefile.mk b/src/soc/amd/common/block/data_fabric/Makefile.mk new file mode 100644 index 0000000000..b0684f4e75 --- /dev/null +++ b/src/soc/amd/common/block/data_fabric/Makefile.mk @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC) += data_fabric_helper.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += domain.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION) += np_region.c + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT),y) +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += pci_segment_multi.c +else +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += pci_segment_single.c +endif + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO),y) +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += extended_mmio.c +else +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += mmio.c +endif diff --git a/src/soc/amd/common/block/emmc/Makefile.inc b/src/soc/amd/common/block/emmc/Makefile.inc deleted file mode 100644 index 3f2603f6e6..0000000000 --- a/src/soc/amd/common/block/emmc/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_EMMC) += emmc.c diff --git a/src/soc/amd/common/block/emmc/Makefile.mk b/src/soc/amd/common/block/emmc/Makefile.mk new file mode 100644 index 0000000000..3f2603f6e6 --- /dev/null +++ b/src/soc/amd/common/block/emmc/Makefile.mk @@ -0,0 +1,2 @@ +## SPDX-License-Identifier: GPL-2.0-only +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_EMMC) += emmc.c diff --git a/src/soc/amd/common/block/gpio/Makefile.inc b/src/soc/amd/common/block/gpio/Makefile.inc deleted file mode 100644 index 3de522e26c..0000000000 --- a/src/soc/amd/common/block/gpio/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS),y) - -all-y += gpio.c -smm-y += gpio.c - -romstage-$(CONFIG_TPM_GOOGLE) += tpm_tis.c -ramstage-$(CONFIG_TPM_GOOGLE) += tpm_tis.c -verstage-$(CONFIG_TPM_GOOGLE) += tpm_tis.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/common/block/gpio/Makefile.mk b/src/soc/amd/common/block/gpio/Makefile.mk new file mode 100644 index 0000000000..3de522e26c --- /dev/null +++ b/src/soc/amd/common/block/gpio/Makefile.mk @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS),y) + +all-y += gpio.c +smm-y += gpio.c + +romstage-$(CONFIG_TPM_GOOGLE) += tpm_tis.c +ramstage-$(CONFIG_TPM_GOOGLE) += tpm_tis.c +verstage-$(CONFIG_TPM_GOOGLE) += tpm_tis.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/common/block/graphics/Makefile.inc b/src/soc/amd/common/block/graphics/Makefile.inc deleted file mode 100644 index 8e3d1bc50a..0000000000 --- a/src/soc/amd/common/block/graphics/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_GRAPHICS) += graphics.c diff --git a/src/soc/amd/common/block/graphics/Makefile.mk b/src/soc/amd/common/block/graphics/Makefile.mk new file mode 100644 index 0000000000..8e3d1bc50a --- /dev/null +++ b/src/soc/amd/common/block/graphics/Makefile.mk @@ -0,0 +1,2 @@ +## SPDX-License-Identifier: GPL-2.0-only +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_GRAPHICS) += graphics.c diff --git a/src/soc/amd/common/block/hda/Makefile.inc b/src/soc/amd/common/block/hda/Makefile.inc deleted file mode 100644 index e21b7582ce..0000000000 --- a/src/soc/amd/common/block/hda/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_HDA) += hda.c diff --git a/src/soc/amd/common/block/hda/Makefile.mk b/src/soc/amd/common/block/hda/Makefile.mk new file mode 100644 index 0000000000..e21b7582ce --- /dev/null +++ b/src/soc/amd/common/block/hda/Makefile.mk @@ -0,0 +1,2 @@ +## SPDX-License-Identifier: GPL-2.0-only +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_HDA) += hda.c diff --git a/src/soc/amd/common/block/i2c/Makefile.inc b/src/soc/amd/common/block/i2c/Makefile.inc deleted file mode 100644 index 2812fb311d..0000000000 --- a/src/soc/amd/common/block/i2c/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C) += i2c.c -all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL) += i2c_pad_ctrl.c -all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL) += i23c_pad_ctrl.c diff --git a/src/soc/amd/common/block/i2c/Makefile.mk b/src/soc/amd/common/block/i2c/Makefile.mk new file mode 100644 index 0000000000..2812fb311d --- /dev/null +++ b/src/soc/amd/common/block/i2c/Makefile.mk @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C) += i2c.c +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL) += i2c_pad_ctrl.c +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL) += i23c_pad_ctrl.c diff --git a/src/soc/amd/common/block/iommu/Makefile.inc b/src/soc/amd/common/block/iommu/Makefile.inc deleted file mode 100644 index a8bc1d6d46..0000000000 --- a/src/soc/amd/common/block/iommu/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_IOMMU) += iommu.c diff --git a/src/soc/amd/common/block/iommu/Makefile.mk b/src/soc/amd/common/block/iommu/Makefile.mk new file mode 100644 index 0000000000..a8bc1d6d46 --- /dev/null +++ b/src/soc/amd/common/block/iommu/Makefile.mk @@ -0,0 +1,2 @@ +## SPDX-License-Identifier: GPL-2.0-only +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_IOMMU) += iommu.c diff --git a/src/soc/amd/common/block/lpc/Makefile.inc b/src/soc/amd/common/block/lpc/Makefile.inc deleted file mode 100644 index 11de514a08..0000000000 --- a/src/soc/amd/common/block/lpc/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC),y) - -ramstage-y += lpc.c - -all_x86-y += lpc_util.c -smm-y += lpc_util.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC - -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) -all_x86-y += spi_dma.c -smm-y += spi_dma.c -endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA - -all-$(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI) += espi_util.c diff --git a/src/soc/amd/common/block/lpc/Makefile.mk b/src/soc/amd/common/block/lpc/Makefile.mk new file mode 100644 index 0000000000..11de514a08 --- /dev/null +++ b/src/soc/amd/common/block/lpc/Makefile.mk @@ -0,0 +1,16 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC),y) + +ramstage-y += lpc.c + +all_x86-y += lpc_util.c +smm-y += lpc_util.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +all_x86-y += spi_dma.c +smm-y += spi_dma.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI) += espi_util.c diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc deleted file mode 100644 index ece43cb67e..0000000000 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ /dev/null @@ -1,15 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y) - -ramstage-y += amd_pci_util.c -ramstage-y += pci_routing_info.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER) += pcie_gpp.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI - -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF),y) - -all_x86-y += amd_pci_mmconf.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF diff --git a/src/soc/amd/common/block/pci/Makefile.mk b/src/soc/amd/common/block/pci/Makefile.mk new file mode 100644 index 0000000000..ece43cb67e --- /dev/null +++ b/src/soc/amd/common/block/pci/Makefile.mk @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y) + +ramstage-y += amd_pci_util.c +ramstage-y += pci_routing_info.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER) += pcie_gpp.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF),y) + +all_x86-y += amd_pci_mmconf.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF diff --git a/src/soc/amd/common/block/pm/Makefile.inc b/src/soc/amd/common/block/pm/Makefile.inc deleted file mode 100644 index cae40994f9..0000000000 --- a/src/soc/amd/common/block/pm/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c - -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c - -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c - -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c diff --git a/src/soc/amd/common/block/pm/Makefile.mk b/src/soc/amd/common/block/pm/Makefile.mk new file mode 100644 index 0000000000..cae40994f9 --- /dev/null +++ b/src/soc/amd/common/block/pm/Makefile.mk @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c + +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c + +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c + +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc deleted file mode 100644 index d0fbcbe452..0000000000 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ /dev/null @@ -1,34 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP),y) - -romstage-y += psp.c -ramstage-y += psp.c -smm-y += psp.c -smm-y += psp_smm.c - -bootblock-y += psp_efs.c -verstage-y += psp_efs.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP - -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y) - -romstage-y += psp_gen1.c -ramstage-y += psp_gen1.c -smm-y += psp_gen1.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1 - -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2),y) - -romstage-y += psp_gen2.c -ramstage-y += psp_gen2.c -ramstage-$(CONFIG_PSP_PLATFORM_SECURE_BOOT) += psb.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) += tpm.c - -smm-y += psp_gen2.c -smm-y += psp_smm_gen2.c - -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SPL) += spl_fuse.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk new file mode 100644 index 0000000000..d0fbcbe452 --- /dev/null +++ b/src/soc/amd/common/block/psp/Makefile.mk @@ -0,0 +1,34 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP),y) + +romstage-y += psp.c +ramstage-y += psp.c +smm-y += psp.c +smm-y += psp_smm.c + +bootblock-y += psp_efs.c +verstage-y += psp_efs.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y) + +romstage-y += psp_gen1.c +ramstage-y += psp_gen1.c +smm-y += psp_gen1.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1 + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2),y) + +romstage-y += psp_gen2.c +ramstage-y += psp_gen2.c +ramstage-$(CONFIG_PSP_PLATFORM_SECURE_BOOT) += psb.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) += tpm.c + +smm-y += psp_gen2.c +smm-y += psp_smm_gen2.c + +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SPL) += spl_fuse.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/common/block/root_complex/Makefile.inc b/src/soc/amd/common/block/root_complex/Makefile.inc deleted file mode 100644 index ba550bda6b..0000000000 --- a/src/soc/amd/common/block/root_complex/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX) += non_pci_resources.c diff --git a/src/soc/amd/common/block/root_complex/Makefile.mk b/src/soc/amd/common/block/root_complex/Makefile.mk new file mode 100644 index 0000000000..ba550bda6b --- /dev/null +++ b/src/soc/amd/common/block/root_complex/Makefile.mk @@ -0,0 +1,2 @@ +## SPDX-License-Identifier: GPL-2.0-only +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX) += non_pci_resources.c diff --git a/src/soc/amd/common/block/sata/Makefile.inc b/src/soc/amd/common/block/sata/Makefile.inc deleted file mode 100644 index 6c735f5598..0000000000 --- a/src/soc/amd/common/block/sata/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SATA) += sata.c diff --git a/src/soc/amd/common/block/sata/Makefile.mk b/src/soc/amd/common/block/sata/Makefile.mk new file mode 100644 index 0000000000..6c735f5598 --- /dev/null +++ b/src/soc/amd/common/block/sata/Makefile.mk @@ -0,0 +1,2 @@ +## SPDX-License-Identifier: GPL-2.0-only +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SATA) += sata.c diff --git a/src/soc/amd/common/block/simnow/Makefile.inc b/src/soc/amd/common/block/simnow/Makefile.inc deleted file mode 100644 index 2cd79c899f..0000000000 --- a/src/soc/amd/common/block/simnow/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_CONSOLE_AMD_SIMNOW),y) -all-y += simnow_console.c - -smm-$(CONFIG_DEBUG_SMI) += simnow_console.c -endif diff --git a/src/soc/amd/common/block/simnow/Makefile.mk b/src/soc/amd/common/block/simnow/Makefile.mk new file mode 100644 index 0000000000..2cd79c899f --- /dev/null +++ b/src/soc/amd/common/block/simnow/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_CONSOLE_AMD_SIMNOW),y) +all-y += simnow_console.c + +smm-$(CONFIG_DEBUG_SMI) += simnow_console.c +endif diff --git a/src/soc/amd/common/block/smbus/Makefile.inc b/src/soc/amd/common/block/smbus/Makefile.inc deleted file mode 100644 index 50b9fdc465..0000000000 --- a/src/soc/amd/common/block/smbus/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMBUS),y) - -bootblock-y += smbus_early_fch.c -romstage-y += smbus.c -ramstage-y += smbus.c -ramstage-y += sm.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMBUS diff --git a/src/soc/amd/common/block/smbus/Makefile.mk b/src/soc/amd/common/block/smbus/Makefile.mk new file mode 100644 index 0000000000..50b9fdc465 --- /dev/null +++ b/src/soc/amd/common/block/smbus/Makefile.mk @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMBUS),y) + +bootblock-y += smbus_early_fch.c +romstage-y += smbus.c +ramstage-y += smbus.c +ramstage-y += sm.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMBUS diff --git a/src/soc/amd/common/block/smi/Makefile.inc b/src/soc/amd/common/block/smi/Makefile.inc deleted file mode 100644 index 0d07f739e3..0000000000 --- a/src/soc/amd/common/block/smi/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMI),y) - -bootblock-y += smi_util.c -romstage-y += smi_util.c -ramstage-y += smi_util.c -smm-y += smi_util.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMI diff --git a/src/soc/amd/common/block/smi/Makefile.mk b/src/soc/amd/common/block/smi/Makefile.mk new file mode 100644 index 0000000000..0d07f739e3 --- /dev/null +++ b/src/soc/amd/common/block/smi/Makefile.mk @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMI),y) + +bootblock-y += smi_util.c +romstage-y += smi_util.c +ramstage-y += smi_util.c +smm-y += smi_util.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMI diff --git a/src/soc/amd/common/block/smn/Makefile.inc b/src/soc/amd/common/block/smn/Makefile.inc deleted file mode 100644 index 12dc4003ad..0000000000 --- a/src/soc/amd/common/block/smn/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMN),y) - -bootblock-y += smn.c -romstage-y += smn.c -ramstage-y += smn.c -smm-y += smn.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMN diff --git a/src/soc/amd/common/block/smn/Makefile.mk b/src/soc/amd/common/block/smn/Makefile.mk new file mode 100644 index 0000000000..12dc4003ad --- /dev/null +++ b/src/soc/amd/common/block/smn/Makefile.mk @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMN),y) + +bootblock-y += smn.c +romstage-y += smn.c +ramstage-y += smn.c +smm-y += smn.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMN diff --git a/src/soc/amd/common/block/smu/Makefile.inc b/src/soc/amd/common/block/smu/Makefile.inc deleted file mode 100644 index 42bdf7006a..0000000000 --- a/src/soc/amd/common/block/smu/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c - -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY) += smu_sx_entry.c diff --git a/src/soc/amd/common/block/smu/Makefile.mk b/src/soc/amd/common/block/smu/Makefile.mk new file mode 100644 index 0000000000..42bdf7006a --- /dev/null +++ b/src/soc/amd/common/block/smu/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c + +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY) += smu_sx_entry.c diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc deleted file mode 100644 index 55ca308c02..0000000000 --- a/src/soc/amd/common/block/spi/Makefile.inc +++ /dev/null @@ -1,25 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI),y) - -bootblock-y += fch_spi_ctrl.c -romstage-y += fch_spi_ctrl.c -verstage-y += fch_spi_ctrl.c -postcar-y += fch_spi_ctrl.c -ramstage-y += fch_spi_ctrl.c -smm-$(CONFIG_SPI_FLASH_SMM) += fch_spi_ctrl.c - -bootblock-y += fch_spi.c -romstage-y += fch_spi.c -postcar-y += fch_spi.c -ramstage-y += fch_spi.c -verstage-y += fch_spi.c -smm-$(CONFIG_SPI_FLASH_SMM) += fch_spi.c - -bootblock-y += fch_spi_util.c -romstage-y += fch_spi_util.c -postcar-y += fch_spi_util.c -ramstage-y += fch_spi_util.c -verstage-y += fch_spi_util.c -smm-$(CONFIG_SPI_FLASH_SMM) += fch_spi_util.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_SPI diff --git a/src/soc/amd/common/block/spi/Makefile.mk b/src/soc/amd/common/block/spi/Makefile.mk new file mode 100644 index 0000000000..55ca308c02 --- /dev/null +++ b/src/soc/amd/common/block/spi/Makefile.mk @@ -0,0 +1,25 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI),y) + +bootblock-y += fch_spi_ctrl.c +romstage-y += fch_spi_ctrl.c +verstage-y += fch_spi_ctrl.c +postcar-y += fch_spi_ctrl.c +ramstage-y += fch_spi_ctrl.c +smm-$(CONFIG_SPI_FLASH_SMM) += fch_spi_ctrl.c + +bootblock-y += fch_spi.c +romstage-y += fch_spi.c +postcar-y += fch_spi.c +ramstage-y += fch_spi.c +verstage-y += fch_spi.c +smm-$(CONFIG_SPI_FLASH_SMM) += fch_spi.c + +bootblock-y += fch_spi_util.c +romstage-y += fch_spi_util.c +postcar-y += fch_spi_util.c +ramstage-y += fch_spi_util.c +verstage-y += fch_spi_util.c +smm-$(CONFIG_SPI_FLASH_SMM) += fch_spi_util.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SPI diff --git a/src/soc/amd/common/block/stb/Makefile.inc b/src/soc/amd/common/block/stb/Makefile.inc deleted file mode 100644 index b77d9650d5..0000000000 --- a/src/soc/amd/common/block/stb/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_STB),y) - -bootblock-y += stb.c -romstage-y += stb.c -ramstage-y += stb.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_STB diff --git a/src/soc/amd/common/block/stb/Makefile.mk b/src/soc/amd/common/block/stb/Makefile.mk new file mode 100644 index 0000000000..b77d9650d5 --- /dev/null +++ b/src/soc/amd/common/block/stb/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_STB),y) + +bootblock-y += stb.c +romstage-y += stb.c +ramstage-y += stb.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_STB diff --git a/src/soc/amd/common/block/uart/Makefile.inc b/src/soc/amd/common/block/uart/Makefile.inc deleted file mode 100644 index bd182d9cb2..0000000000 --- a/src/soc/amd/common/block/uart/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UART),y) - -all_x86-y += uart.c -smm-$(CONFIG_DEBUG_SMI) += uart.c - -all-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c - -ifeq ($(CONFIG_DEBUG_SMI),y) -smm-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c -endif - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_UART diff --git a/src/soc/amd/common/block/uart/Makefile.mk b/src/soc/amd/common/block/uart/Makefile.mk new file mode 100644 index 0000000000..bd182d9cb2 --- /dev/null +++ b/src/soc/amd/common/block/uart/Makefile.mk @@ -0,0 +1,13 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UART),y) + +all_x86-y += uart.c +smm-$(CONFIG_DEBUG_SMI) += uart.c + +all-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c + +ifeq ($(CONFIG_DEBUG_SMI),y) +smm-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c +endif + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_UART diff --git a/src/soc/amd/common/block/xhci/Makefile.inc b/src/soc/amd/common/block/xhci/Makefile.inc deleted file mode 100644 index 377ca2740a..0000000000 --- a/src/soc/amd/common/block/xhci/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_XHCI) += xhci.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_XHCI_ELOG) += elog.c diff --git a/src/soc/amd/common/block/xhci/Makefile.mk b/src/soc/amd/common/block/xhci/Makefile.mk new file mode 100644 index 0000000000..377ca2740a --- /dev/null +++ b/src/soc/amd/common/block/xhci/Makefile.mk @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_XHCI) += xhci.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_XHCI_ELOG) += elog.c diff --git a/src/soc/amd/common/fsp/Makefile.inc b/src/soc/amd/common/fsp/Makefile.inc deleted file mode 100644 index fb78f52925..0000000000 --- a/src/soc/amd/common/fsp/Makefile.inc +++ /dev/null @@ -1,28 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) -romstage-y += fsp_memmap.c -romstage-y += fsp_reset.c -romstage-y += fsp_romstage.c -romstage-y += fsp_validate.c -ramstage-y += fsp_graphics.c -ramstage-y += fsp_memmap.c -ramstage-y += fsp_ramstage.c -ramstage-y += fsp_report_resources.c -ramstage-y += fsp_reset.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fsp-acpi.c -ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_CCX_CPPC_HOB) += fsp_ccx_cppc_hob.c -ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_DMI_TABLES) += dmi.c -ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PRELOAD_FSPS) += preload_fsps.c - -subdirs-y += ./* - -ifeq ($(CONFIG_ADD_FSP_BINARIES),y) -ifeq ($(call int-gt,\ - $(call file-size,$(CONFIG_FSP_M_FILE))\ - $(shell printf "%d" $(CONFIG_FSP_M_SIZE))),\ - 1) -$(error FSP-M binary larger than FSP_M_SIZE.) -endif -endif # CONFIG_ADD_FSP_BINARIES - -endif # CONFIG_PLATFORM_USES_FSP2_0 diff --git a/src/soc/amd/common/fsp/Makefile.mk b/src/soc/amd/common/fsp/Makefile.mk new file mode 100644 index 0000000000..fb78f52925 --- /dev/null +++ b/src/soc/amd/common/fsp/Makefile.mk @@ -0,0 +1,28 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +romstage-y += fsp_memmap.c +romstage-y += fsp_reset.c +romstage-y += fsp_romstage.c +romstage-y += fsp_validate.c +ramstage-y += fsp_graphics.c +ramstage-y += fsp_memmap.c +ramstage-y += fsp_ramstage.c +ramstage-y += fsp_report_resources.c +ramstage-y += fsp_reset.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fsp-acpi.c +ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_CCX_CPPC_HOB) += fsp_ccx_cppc_hob.c +ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_DMI_TABLES) += dmi.c +ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PRELOAD_FSPS) += preload_fsps.c + +subdirs-y += ./* + +ifeq ($(CONFIG_ADD_FSP_BINARIES),y) +ifeq ($(call int-gt,\ + $(call file-size,$(CONFIG_FSP_M_FILE))\ + $(shell printf "%d" $(CONFIG_FSP_M_SIZE))),\ + 1) +$(error FSP-M binary larger than FSP_M_SIZE.) +endif +endif # CONFIG_ADD_FSP_BINARIES + +endif # CONFIG_PLATFORM_USES_FSP2_0 diff --git a/src/soc/amd/common/fsp/pci/Makefile.inc b/src/soc/amd/common/fsp/pci/Makefile.inc deleted file mode 100644 index e0b2cd97a7..0000000000 --- a/src/soc/amd/common/fsp/pci/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PCI) += pci_routing_info.c - -ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PCIE_CLK_REQ) += pcie_clk_req.c diff --git a/src/soc/amd/common/fsp/pci/Makefile.mk b/src/soc/amd/common/fsp/pci/Makefile.mk new file mode 100644 index 0000000000..e0b2cd97a7 --- /dev/null +++ b/src/soc/amd/common/fsp/pci/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PCI) += pci_routing_info.c + +ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PCIE_CLK_REQ) += pcie_clk_req.c diff --git a/src/soc/amd/common/pi/Makefile.inc b/src/soc/amd/common/pi/Makefile.inc deleted file mode 100644 index 8fcc4c0cf4..0000000000 --- a/src/soc/amd/common/pi/Makefile.inc +++ /dev/null @@ -1,23 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_PI),y) - -romstage-y += agesawrapper.c -romstage-y += def_callouts.c -romstage-y += heapmanager.c -romstage-y += image.c -romstage-y += refcode_loader.c -romstage-y += s3_resume.c - -ramstage-y += agesawrapper.c -ramstage-y += amd_late_init.c -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += amd_resume_final.c -ramstage-y += def_callouts.c -ramstage-y += heapmanager.c -ramstage-y += image.c -ramstage-y += refcode_loader.c -ramstage-y += s3_resume.c - -CFLAGS_x86_32 += -Wno-pragma-pack -CFLAGS_x86_64 += -Wno-pragma-pack - -endif # CONFIG_SOC_AMD_PI diff --git a/src/soc/amd/common/pi/Makefile.mk b/src/soc/amd/common/pi/Makefile.mk new file mode 100644 index 0000000000..8fcc4c0cf4 --- /dev/null +++ b/src/soc/amd/common/pi/Makefile.mk @@ -0,0 +1,23 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_PI),y) + +romstage-y += agesawrapper.c +romstage-y += def_callouts.c +romstage-y += heapmanager.c +romstage-y += image.c +romstage-y += refcode_loader.c +romstage-y += s3_resume.c + +ramstage-y += agesawrapper.c +ramstage-y += amd_late_init.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += amd_resume_final.c +ramstage-y += def_callouts.c +ramstage-y += heapmanager.c +ramstage-y += image.c +ramstage-y += refcode_loader.c +ramstage-y += s3_resume.c + +CFLAGS_x86_32 += -Wno-pragma-pack +CFLAGS_x86_64 += -Wno-pragma-pack + +endif # CONFIG_SOC_AMD_PI diff --git a/src/soc/amd/common/psp_verstage/Makefile.inc b/src/soc/amd/common/psp_verstage/Makefile.inc deleted file mode 100644 index ee71d9930e..0000000000 --- a/src/soc/amd/common/psp_verstage/Makefile.inc +++ /dev/null @@ -1,34 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include -verstage-generic-ccopts += -D__USER_SPACE__ -CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/2lib/include/ - -ifeq ($(CONFIG_COMPILER_GCC),y) -# This size should match the size in the linker script. -CFLAGS_arm += -Wstack-usage=40960 -else -CFLAGS_arm += -Wframe-larger-than=40960 -endif - -verstage-y += boot_dev.c -verstage-y += delay.c -verstage-y += fch.c -verstage-y += pmutil.c -verstage-y += post.c -verstage-y += printk.c -verstage-y += psp_verstage.c -verstage-y += psp.c -verstage-y += reset.c -verstage-y += timer.c -verstage-y += vboot_crypto.c - -$(obj)/psp_verstage.bin: $(objcbfs)/verstage.elf - $(OBJCOPY_verstage) -O binary $^ $@ - -# Default CONFIG_PSP_VERSTAGE_FILE configuration requires psp_verstage.bin and the above -# build rule takes effect. Once CONFIG_PSP_VERSTAGE_FILE is overridden with signed PSP -# verstage, then psp_verstage.bin is not built. The following build rule ensures that the -# unsigned psp_verstage.bin is still built even when not used so that it can be used for -# signing purposes. -build_complete:: $(obj)/psp_verstage.bin diff --git a/src/soc/amd/common/psp_verstage/Makefile.mk b/src/soc/amd/common/psp_verstage/Makefile.mk new file mode 100644 index 0000000000..ee71d9930e --- /dev/null +++ b/src/soc/amd/common/psp_verstage/Makefile.mk @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only + +verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include +verstage-generic-ccopts += -D__USER_SPACE__ +CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/2lib/include/ + +ifeq ($(CONFIG_COMPILER_GCC),y) +# This size should match the size in the linker script. +CFLAGS_arm += -Wstack-usage=40960 +else +CFLAGS_arm += -Wframe-larger-than=40960 +endif + +verstage-y += boot_dev.c +verstage-y += delay.c +verstage-y += fch.c +verstage-y += pmutil.c +verstage-y += post.c +verstage-y += printk.c +verstage-y += psp_verstage.c +verstage-y += psp.c +verstage-y += reset.c +verstage-y += timer.c +verstage-y += vboot_crypto.c + +$(obj)/psp_verstage.bin: $(objcbfs)/verstage.elf + $(OBJCOPY_verstage) -O binary $^ $@ + +# Default CONFIG_PSP_VERSTAGE_FILE configuration requires psp_verstage.bin and the above +# build rule takes effect. Once CONFIG_PSP_VERSTAGE_FILE is overridden with signed PSP +# verstage, then psp_verstage.bin is not built. The following build rule ensures that the +# unsigned psp_verstage.bin is still built even when not used so that it can be used for +# signing purposes. +build_complete:: $(obj)/psp_verstage.bin diff --git a/src/soc/amd/common/vboot/Makefile.inc b/src/soc/amd/common/vboot/Makefile.inc deleted file mode 100644 index c40a6b0555..0000000000 --- a/src/soc/amd/common/vboot/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_VBOOT_VBNV_CMOS),y) -bootblock-y += vbnv_cmos.c -verstage-y += vbnv_cmos.c -romstage-y += vbnv_cmos.c -ramstage-y += vbnv_cmos.c -endif - -bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += vboot_bootblock.c -bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += transfer_buffer.c -smm-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += transfer_buffer.c - -# We don't use the early RAM memlayout linker for SMM, so we don't have access -# to the early RAM symbols. We manually generate a file that defines the symbols -# for us. -$(obj)/smm/early_ram_symbols.ld: $(objcbfs)/bootblock.map $(src)/soc/amd/common/vboot/early_ram_symbols.awk - awk -f $(src)/soc/amd/common/vboot/early_ram_symbols.awk -- "$<" > "$@" - -$(obj)/smm/smm.elf: $(obj)/smm/early_ram_symbols.ld -$(obj)/smm/smm.elf-ldflags += -T $(obj)/smm/early_ram_symbols.ld diff --git a/src/soc/amd/common/vboot/Makefile.mk b/src/soc/amd/common/vboot/Makefile.mk new file mode 100644 index 0000000000..c40a6b0555 --- /dev/null +++ b/src/soc/amd/common/vboot/Makefile.mk @@ -0,0 +1,20 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_VBOOT_VBNV_CMOS),y) +bootblock-y += vbnv_cmos.c +verstage-y += vbnv_cmos.c +romstage-y += vbnv_cmos.c +ramstage-y += vbnv_cmos.c +endif + +bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += vboot_bootblock.c +bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += transfer_buffer.c +smm-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += transfer_buffer.c + +# We don't use the early RAM memlayout linker for SMM, so we don't have access +# to the early RAM symbols. We manually generate a file that defines the symbols +# for us. +$(obj)/smm/early_ram_symbols.ld: $(objcbfs)/bootblock.map $(src)/soc/amd/common/vboot/early_ram_symbols.awk + awk -f $(src)/soc/amd/common/vboot/early_ram_symbols.awk -- "$<" > "$@" + +$(obj)/smm/smm.elf: $(obj)/smm/early_ram_symbols.ld +$(obj)/smm/smm.elf-ldflags += -T $(obj)/smm/early_ram_symbols.ld diff --git a/src/soc/amd/genoa_poc/Makefile.inc b/src/soc/amd/genoa_poc/Makefile.inc deleted file mode 100644 index 01bbe7b8f9..0000000000 --- a/src/soc/amd/genoa_poc/Makefile.inc +++ /dev/null @@ -1,151 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_GENOA_POC),y) - -all-y += mmap_boot.c -all-y += reset.c -all-y += config.c -all-y += gpio.c -all-y += i2c.c -all-y += uart.c - -bootblock-y += early_fch.c -bootblock-y += aoac.c - -ramstage-y += acpi.c -ramstage-y += aoac.c -ramstage-y += chip.c -ramstage-y += cpu.c -ramstage-y += domain.c -ramstage-y += fch.c -ramstage-y += root_complex.c -ramstage-y += smihandler.c -ramstage-y += mca.c - -smm-y += smihandler.c - -CPPFLAGS_common += -I$(src)/soc/amd/genoa_poc/acpi -CPPFLAGS_common += -I$(src)/soc/amd/genoa_poc/include - -ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1) -CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000 -endif - -# -# PSP Directory Table items -# -# Certain ordering requirements apply, however these are ensured by amdfwtool. -# For more information see "AMD Platform Security Processor BIOS Implementation -# Guide for Server EPYC Processors" #57299 -# - -FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') - -ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) -PSP_SOFTFUSE_BITS += 7 -endif - -ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) -# Enable secure debug unlock -PSP_SOFTFUSE_BITS += 0 -OPT_TOKEN_UNLOCK="--token-unlock" -endif - -# Use additional Soft Fuse bits specified in Kconfig -PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) - -# type = 0x3a -ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) -PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) -endif - -# type = 0x55 -SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) - -# -# BIOS Directory Table items - proper ordering is managed by amdfwtool -# - -# type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) $(APCB1_SOURCES) $(APCB_SOURCES_RECOVERY) $(APCB_SOURCES_RECOVERY1) $(APCB_SOURCES_RECOVERY2) - -# type = 0x61 -PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) - -# type = 0x62 -PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img -PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') - -# Helper function to return a value with given bit set -# Soft Fuse type = 0xb - See #57299 (NDA) for bit definitions. -set-bit=$(call int-shift-left, 1 $(call _toint,$1)) -PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) - -# -# Build the arguments to amdfwtool (order is unimportant). Missing file names -# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. -# - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ - $(if $(APCB_SOURCES1), --instance 1 --apcb $(APCB_SOURCES1)) \ - $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ - $(if $(APCB_SOURCES_RECOVERY1), --instance 18 --apcb $(APCB_SOURCES_RECOVERY1)) \ - $(if $(APCB_SOURCES_RECOVERY2), --instance 19 --apcb $(APCB_SOURCES_RECOVERY2)) \ - $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) - -OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) -OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) -OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) -OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) - -OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) -OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) -OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) -OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) - -OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) -OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) - -AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ - $(OPT_APOB_ADDR) \ - $(OPT_DEBUG_AMDFWTOOL) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - $(OPT_PSP_SOFTFUSE) \ - --use-pspsecureos \ - $(OPT_TOKEN_UNLOCK) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_SPL_TABLE_FILE) \ - $(OPT_EFS_SPI_READ_MODE) \ - $(OPT_EFS_SPI_SPEED) \ - $(OPT_EFS_SPI_MICRON_FLAG) \ - --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --flashsize 0x1000000 - -$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ - $$(PSP_APCB_FILES) \ - $(DEP_FILES) \ - $(AMDFWTOOL) \ - $(obj)/fmap_config.h \ - $(objcbfs)/bootblock.elf # this target also creates the .map file - $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - --location $(CONFIG_AMD_FWM_POSITION) \ - --multilevel \ - --output $@ - -$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) - rm -f $@ - @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) - -endif diff --git a/src/soc/amd/genoa_poc/Makefile.mk b/src/soc/amd/genoa_poc/Makefile.mk new file mode 100644 index 0000000000..01bbe7b8f9 --- /dev/null +++ b/src/soc/amd/genoa_poc/Makefile.mk @@ -0,0 +1,151 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_GENOA_POC),y) + +all-y += mmap_boot.c +all-y += reset.c +all-y += config.c +all-y += gpio.c +all-y += i2c.c +all-y += uart.c + +bootblock-y += early_fch.c +bootblock-y += aoac.c + +ramstage-y += acpi.c +ramstage-y += aoac.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += domain.c +ramstage-y += fch.c +ramstage-y += root_complex.c +ramstage-y += smihandler.c +ramstage-y += mca.c + +smm-y += smihandler.c + +CPPFLAGS_common += -I$(src)/soc/amd/genoa_poc/acpi +CPPFLAGS_common += -I$(src)/soc/amd/genoa_poc/include + +ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1) +CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000 +endif + +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Implementation +# Guide for Server EPYC Processors" #57299 +# + +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') + +ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) +PSP_SOFTFUSE_BITS += 7 +endif + +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" +endif + +# Use additional Soft Fuse bits specified in Kconfig +PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif + +# type = 0x55 +SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) $(APCB1_SOURCES) $(APCB_SOURCES_RECOVERY) $(APCB_SOURCES_RECOVERY1) $(APCB_SOURCES_RECOVERY2) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') + +# Helper function to return a value with given bit set +# Soft Fuse type = 0xb - See #57299 (NDA) for bit definitions. +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ + $(if $(APCB_SOURCES1), --instance 1 --apcb $(APCB_SOURCES1)) \ + $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ + $(if $(APCB_SOURCES_RECOVERY1), --instance 18 --apcb $(APCB_SOURCES_RECOVERY1)) \ + $(if $(APCB_SOURCES_RECOVERY2), --instance 19 --apcb $(APCB_SOURCES_RECOVERY2)) \ + $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + $(OPT_DEBUG_AMDFWTOOL) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + --use-pspsecureos \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_SPL_TABLE_FILE) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --flashsize 0x1000000 + +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ + $(AMDFWTOOL) \ + $(obj)/fmap_config.h \ + $(objcbfs)/bootblock.elf # this target also creates the .map file + $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + --location $(CONFIG_AMD_FWM_POSITION) \ + --multilevel \ + --output $@ + +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + +endif diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc deleted file mode 100644 index bc217d36d1..0000000000 --- a/src/soc/amd/glinda/Makefile.inc +++ /dev/null @@ -1,292 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -# TODO: Move as much as possible to common -# TODO: Update for Glinda - -ifeq ($(CONFIG_SOC_AMD_GLINDA),y) - -subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage - -# Beware that all-y also adds the compilation unit to verstage on PSP -all-y += aoac.c -all-y += config.c -all-y += i2c.c - -# all_x86-y adds the compilation unit to all stages that run on the x86 cores -all_x86-y += gpio.c -all_x86-y += uart.c - -bootblock-y += early_fch.c -bootblock-y += espi_util.c - -verstage-y += espi_util.c - -romstage-y += fsp_m_params.c - -ramstage-y += acpi.c -ramstage-y += agesa_acpi.c -ramstage-y += chip.c -ramstage-y += cpu.c -ramstage-y += fch.c -ramstage-y += fsp_s_params.c -ramstage-y += mca.c -ramstage-y += root_complex.c -ramstage-y += xhci.c - -smm-y += gpio.c -smm-y += smihandler.c -smm-$(CONFIG_DEBUG_SMI) += uart.c - -CPPFLAGS_common += -I$(src)/soc/amd/glinda/include -CPPFLAGS_common += -I$(src)/soc/amd/glinda/acpi -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/glinda -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common - -# Building the cbfs image will fail if the offset, aligned to 64 bytes, isn't large enough -ifeq ($(CONFIG_CBFS_VERIFICATION),y) -# 0x80 accounts for the cbfs_file struct + filename + metadata structs -AMD_FW_AB_POSITION := 0x80 -else # ($(CONFIG_CBFS_VERIFICATION), y) -# 0x40 accounts for the cbfs_file struct + filename + metadata structs without hash attribute -AMD_FW_AB_POSITION := 0x40 -endif # ($(CONFIG_CBFS_VERIFICATION), y) - -GLINDA_FW_A_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) - -GLINDA_FW_B_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) -# -# PSP Directory Table items -# -# Certain ordering requirements apply, however these are ensured by amdfwtool. -# For more information see "AMD Platform Security Processor BIOS Architecture -# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). -# - -ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) -PSP_SOFTFUSE_BITS += 7 -endif - -ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) -# Enable secure debug unlock -PSP_SOFTFUSE_BITS += 0 -OPT_TOKEN_UNLOCK="--token-unlock" -endif - -ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) -OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" -else -# Disable MP2 firmware loading -PSP_SOFTFUSE_BITS += 29 -endif - -# Use additional Soft Fuse bits specified in Kconfig -PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) - -# type = 0x3a -ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) -PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) -endif - -# type = 0x55 -SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) -SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) -else -SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -endif - -# -# BIOS Directory Table items - proper ordering is managed by amdfwtool -# - -# type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) - -# type = 0x61 -PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) - -# type = 0x62 -PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img -PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') - -ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) -# type = 0x63 - construct APOB NV base/size from flash map -# The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) -APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) -endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# type = 0x6B - PSP Shared memory location -ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) -PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) -PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) -endif - -# type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) -PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) -endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK - -ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) -SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ - $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) \ - $(call get_fmap_value,FMAP_SECTION_FLASH_START)) -SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ - $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) \ - $(call get_fmap_value,FMAP_SECTION_FLASH_START)) -SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed -SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed -endif # CONFIG_SEPARATE_SIGNED_PSPFW - -# Helper function to return a value with given bit set -# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. -set-bit=$(call int-shift-left, 1 $(call _toint,$1)) -PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) - -# -# Build the arguments to amdfwtool (order is unimportant). Missing file names -# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. -# - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) -OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) - -OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ - $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ - $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) - -OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) -OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) -OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) -OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) - -OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) -OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) -OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) -OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) -OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) -OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) -OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) - -OPT_SIGNED_AMDFW_A_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_A_POSITION), --signed-addr) -OPT_SIGNED_AMDFW_A_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_A_FILE), --signed-output) -OPT_SIGNED_AMDFW_B_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_B_POSITION), --signed-addr) -OPT_SIGNED_AMDFW_B_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_B_FILE), --signed-output) - -OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) - -OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) -OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) -OPT_SPL_RW_AB_TABLE_FILE=$(call add_opt_prefix, $(SPL_RW_AB_TABLE_FILE), --spl-table) - -# If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant -OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) - -AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ - $(OPT_APOB_ADDR) \ - $(OPT_DEBUG_AMDFWTOOL) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_LOAD_MP2_FW) \ - --use-pspsecureos \ - --load-s0i3 \ - $(OPT_TOKEN_UNLOCK) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_PSP_SHAREDMEM_BASE) \ - $(OPT_PSP_SHAREDMEM_SIZE) \ - $(OPT_EFS_SPI_READ_MODE) \ - $(OPT_EFS_SPI_SPEED) \ - $(OPT_EFS_SPI_MICRON_FLAG) \ - --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --flashsize $(CONFIG_ROM_SIZE) \ - $(OPT_RECOVERY_AB_SINGLE_COPY) - -$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ - $(PSP_VERSTAGE_FILE) \ - $(PSP_VERSTAGE_SIG_FILE) \ - $$(PSP_APCB_FILES) \ - $(DEP_FILES) \ - $(AMDFWTOOL) \ - $(obj)/fmap_config.h \ - $(objcbfs)/bootblock.elf # this target also creates the .map file - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - $(OPT_VERSTAGE_FILE) \ - $(OPT_VERSTAGE_SIG_FILE) \ - $(OPT_SPL_TABLE_FILE) \ - --location $(CONFIG_AMD_FWM_POSITION) \ - --output $@ - -$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) - rm -f $@ - @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) - -$(obj)/amdfw_a.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - $(OPT_SPL_RW_AB_TABLE_FILE) \ - $(OPT_SIGNED_AMDFW_A_POSITION) \ - $(OPT_SIGNED_AMDFW_A_FILE) \ - --location $(call _tohex,$(GLINDA_FW_A_POSITION)) \ - --anywhere \ - --output $@ - -$(obj)/amdfw_b.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - $(OPT_SPL_RW_AB_TABLE_FILE) \ - $(OPT_SIGNED_AMDFW_B_POSITION) \ - $(OPT_SIGNED_AMDFW_B_FILE) \ - --location $(call _tohex,$(GLINDA_FW_B_POSITION)) \ - --anywhere \ - --output $@ - - -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -cbfs-files-y += apu/amdfw_a -apu/amdfw_a-file := $(obj)/amdfw_a.rom -apu/amdfw_a-position := $(AMD_FW_AB_POSITION) -apu/amdfw_a-type := raw - -cbfs-files-y += apu/amdfw_b -apu/amdfw_b-file := $(obj)/amdfw_b.rom -apu/amdfw_b-position := $(AMD_FW_AB_POSITION) -apu/amdfw_b-type := raw - -ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) -build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom - @printf " Adding Signed ROM and HASH\n" - $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed - $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.signed - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f $(obj)/amdfw_a.rom.signed.hash \ - -n apu/amdfw_a_hash -t raw - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.signed.hash \ - -n apu/amdfw_b_hash -t raw -endif # CONFIG_SEPARATE_SIGNED_PSPFW -endif - -endif # ($(CONFIG_SOC_AMD_GLINDA),y) diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk new file mode 100644 index 0000000000..bc217d36d1 --- /dev/null +++ b/src/soc/amd/glinda/Makefile.mk @@ -0,0 +1,292 @@ +# SPDX-License-Identifier: BSD-3-Clause + +# TODO: Move as much as possible to common +# TODO: Update for Glinda + +ifeq ($(CONFIG_SOC_AMD_GLINDA),y) + +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage + +# Beware that all-y also adds the compilation unit to verstage on PSP +all-y += aoac.c +all-y += config.c +all-y += i2c.c + +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + +bootblock-y += early_fch.c +bootblock-y += espi_util.c + +verstage-y += espi_util.c + +romstage-y += fsp_m_params.c + +ramstage-y += acpi.c +ramstage-y += agesa_acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += fch.c +ramstage-y += fsp_s_params.c +ramstage-y += mca.c +ramstage-y += root_complex.c +ramstage-y += xhci.c + +smm-y += gpio.c +smm-y += smihandler.c +smm-$(CONFIG_DEBUG_SMI) += uart.c + +CPPFLAGS_common += -I$(src)/soc/amd/glinda/include +CPPFLAGS_common += -I$(src)/soc/amd/glinda/acpi +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/glinda +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common + +# Building the cbfs image will fail if the offset, aligned to 64 bytes, isn't large enough +ifeq ($(CONFIG_CBFS_VERIFICATION),y) +# 0x80 accounts for the cbfs_file struct + filename + metadata structs +AMD_FW_AB_POSITION := 0x80 +else # ($(CONFIG_CBFS_VERIFICATION), y) +# 0x40 accounts for the cbfs_file struct + filename + metadata structs without hash attribute +AMD_FW_AB_POSITION := 0x40 +endif # ($(CONFIG_CBFS_VERIFICATION), y) + +GLINDA_FW_A_POSITION=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) + +GLINDA_FW_B_POSITION=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Architecture +# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). +# + +ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) +PSP_SOFTFUSE_BITS += 7 +endif + +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" +endif + +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" +else +# Disable MP2 firmware loading +PSP_SOFTFUSE_BITS += 29 +endif + +# Use additional Soft Fuse bits specified in Kconfig +PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif + +# type = 0x55 +SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) +ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) +SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) +else +SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) +endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') + +ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) +# type = 0x63 - construct APOB NV base/size from flash map +# The flashmap section used for this is expected to be named RW_MRC_CACHE +APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) +endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +# type = 0x6B - PSP Shared memory location +ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) +PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) +PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) +endif + +# type = 0x52 - PSP Bootloader Userspace Application (verstage) +PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) +PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) +endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK + +ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) +SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ + $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) \ + $(call get_fmap_value,FMAP_SECTION_FLASH_START)) +SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ + $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) \ + $(call get_fmap_value,FMAP_SECTION_FLASH_START)) +SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed +SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed +endif # CONFIG_SEPARATE_SIGNED_PSPFW + +# Helper function to return a value with given bit set +# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) +OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) + +OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ + $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ + $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) +OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) +OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) +OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) + +OPT_SIGNED_AMDFW_A_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_A_POSITION), --signed-addr) +OPT_SIGNED_AMDFW_A_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_A_FILE), --signed-output) +OPT_SIGNED_AMDFW_B_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_B_POSITION), --signed-addr) +OPT_SIGNED_AMDFW_B_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_B_FILE), --signed-output) + +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) +OPT_SPL_RW_AB_TABLE_FILE=$(call add_opt_prefix, $(SPL_RW_AB_TABLE_FILE), --spl-table) + +# If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant +OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + $(OPT_DEBUG_AMDFWTOOL) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + $(OPT_PSP_LOAD_MP2_FW) \ + --use-pspsecureos \ + --load-s0i3 \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --flashsize $(CONFIG_ROM_SIZE) \ + $(OPT_RECOVERY_AB_SINGLE_COPY) + +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $(PSP_VERSTAGE_FILE) \ + $(PSP_VERSTAGE_SIG_FILE) \ + $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ + $(AMDFWTOOL) \ + $(obj)/fmap_config.h \ + $(objcbfs)/bootblock.elf # this target also creates the .map file + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ + $(OPT_SPL_TABLE_FILE) \ + --location $(CONFIG_AMD_FWM_POSITION) \ + --output $@ + +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + +$(obj)/amdfw_a.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + $(OPT_SPL_RW_AB_TABLE_FILE) \ + $(OPT_SIGNED_AMDFW_A_POSITION) \ + $(OPT_SIGNED_AMDFW_A_FILE) \ + --location $(call _tohex,$(GLINDA_FW_A_POSITION)) \ + --anywhere \ + --output $@ + +$(obj)/amdfw_b.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + $(OPT_SPL_RW_AB_TABLE_FILE) \ + $(OPT_SIGNED_AMDFW_B_POSITION) \ + $(OPT_SIGNED_AMDFW_B_FILE) \ + --location $(call _tohex,$(GLINDA_FW_B_POSITION)) \ + --anywhere \ + --output $@ + + +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_a +apu/amdfw_a-file := $(obj)/amdfw_a.rom +apu/amdfw_a-position := $(AMD_FW_AB_POSITION) +apu/amdfw_a-type := raw + +cbfs-files-y += apu/amdfw_b +apu/amdfw_b-file := $(obj)/amdfw_b.rom +apu/amdfw_b-position := $(AMD_FW_AB_POSITION) +apu/amdfw_b-type := raw + +ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) +build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom + @printf " Adding Signed ROM and HASH\n" + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.signed + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f $(obj)/amdfw_a.rom.signed.hash \ + -n apu/amdfw_a_hash -t raw + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.signed.hash \ + -n apu/amdfw_b_hash -t raw +endif # CONFIG_SEPARATE_SIGNED_PSPFW +endif + +endif # ($(CONFIG_SOC_AMD_GLINDA),y) diff --git a/src/soc/amd/glinda/psp_verstage/Makefile.inc b/src/soc/amd/glinda/psp_verstage/Makefile.inc deleted file mode 100644 index 472ca2d3d2..0000000000 --- a/src/soc/amd/glinda/psp_verstage/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -ifeq $($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) - -subdirs-y += ../../common/psp_verstage - -verstage-generic-ccopts += -I$(src)/soc/amd/glinda/psp_verstage/include -verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include -verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/glinda/include -verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/common/include - -verstage-y += svc.c -verstage-y += chipset.c -verstage-y += uart.c - -verstage-y +=$(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S -verstage-y += $(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S - -endif diff --git a/src/soc/amd/glinda/psp_verstage/Makefile.mk b/src/soc/amd/glinda/psp_verstage/Makefile.mk new file mode 100644 index 0000000000..472ca2d3d2 --- /dev/null +++ b/src/soc/amd/glinda/psp_verstage/Makefile.mk @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ifeq $($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) + +subdirs-y += ../../common/psp_verstage + +verstage-generic-ccopts += -I$(src)/soc/amd/glinda/psp_verstage/include +verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include +verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/glinda/include +verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/common/include + +verstage-y += svc.c +verstage-y += chipset.c +verstage-y += uart.c + +verstage-y +=$(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S + +endif diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc deleted file mode 100644 index 5b9216e638..0000000000 --- a/src/soc/amd/mendocino/Makefile.inc +++ /dev/null @@ -1,366 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -ifeq ($(CONFIG_SOC_AMD_MENDOCINO),y) - -subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage - -# Beware that all-y also adds the compilation unit to verstage on PSP -all-y += aoac.c -all-y += config.c -all-y += i2c.c - -# all_x86-y adds the compilation unit to all stages that run on the x86 cores -all_x86-y += gpio.c -all_x86-y += uart.c - -bootblock-y += early_fch.c -bootblock-y += espi_util.c - -verstage-y += espi_util.c - -romstage-y += fsp_m_params.c - -ramstage-y += acpi.c -ramstage-y += agesa_acpi.c -ramstage-y += chip.c -ramstage-y += cpu.c -ramstage-y += fch.c -ramstage-y += fsp_misc_data_hob.c -ramstage-y += fsp_s_params.c -ramstage-y += mca.c -ramstage-y += root_complex.c -ramstage-y += xhci.c -ramstage-y += manifest.c - -smm-y += gpio.c -smm-y += smihandler.c -smm-$(CONFIG_DEBUG_SMI) += uart.c - -CPPFLAGS_common += -I$(src)/soc/amd/mendocino/include -CPPFLAGS_common += -I$(src)/soc/amd/mendocino/acpi -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/mendocino -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common - -# Building the cbfs image will fail if the offset, aligned to 64 bytes, isn't large enough -ifeq ($(CONFIG_CBFS_VERIFICATION),y) -# 0x80 accounts for the cbfs_file struct + filename + metadata structs -AMD_FW_AB_POSITION := 0x80 -else # ($(CONFIG_CBFS_VERIFICATION), y) -# 0x40 accounts for the cbfs_file struct + filename + metadata structs without hash attribute -AMD_FW_AB_POSITION := 0x40 -endif # ($(CONFIG_CBFS_VERIFICATION), y) - -MENDOCINO_FW_A_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) - -MENDOCINO_FW_B_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) - -MENDOCINO_FW_BODY_OFFSET := 0x100 - -# -# PSP Directory Table items -# -# Certain ordering requirements apply, however these are ensured by amdfwtool. -# For more information see "AMD Platform Security Processor BIOS Architecture -# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). -# - -ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) -PSP_SOFTFUSE_BITS += 7 -endif - -ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) -# Enable secure debug unlock -PSP_SOFTFUSE_BITS += 0 -OPT_TOKEN_UNLOCK="--token-unlock" -endif - -ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) -OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" -else -# Disable MP2 firmware loading -PSP_SOFTFUSE_BITS += 29 -endif - -# Use additional Soft Fuse bits specified in Kconfig -PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) -PSP_RO_SOFTFUSE_BITS=$(PSP_SOFTFUSE_BITS) - -# type = 0x3a -ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) -PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) -endif - -# type = 0x55 -SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) -SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) -else -SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -endif - -# -# BIOS Directory Table items - proper ordering is managed by amdfwtool -# - -# type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) - -# type = 0x61 -PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) - -# type = 0x62 -PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img -PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') - -ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) -# type = 0x63 - construct APOB NV base/size from flash map -# The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) -APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) - -ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y) -# On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE. -# Else use RW_MRC_CACHE. This entry will be added in the RO section. -APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE) -APOB_NV_RO_BASE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_START) -else -APOB_NV_RO_SIZE=$(APOB_NV_SIZE) -APOB_NV_RO_BASE=$(APOB_NV_BASE) -endif -endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# type = 0x6B - PSP Shared memory location -ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) -PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) -PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) -endif - -# type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) -PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) -endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK - -ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) -SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ - $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) \ - $(call get_fmap_value,FMAP_SECTION_FLASH_START)) -SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ - $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) \ - $(call get_fmap_value,FMAP_SECTION_FLASH_START)) -SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.body.signed -SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.body.signed -endif # CONFIG_SEPARATE_SIGNED_PSPFW - -# Helper function to return a value with given bit set -# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. -set-bit=$(call int-shift-left, 1 $(call _toint,$1)) -PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) -PSP_RO_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(sort $(PSP_RO_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) - -# -# Build the arguments to amdfwtool (order is unimportant). Missing file names -# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. -# - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) -OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) - -OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ - $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ - $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) - -OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) -OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) -OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) -OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) - -OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) -OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) -OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) -OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) -OPT_APOB_NV_RO_SIZE=$(call add_opt_prefix, $(APOB_NV_RO_SIZE), --apob-nv-size) -OPT_APOB_NV_RO_BASE=$(call add_opt_prefix, $(APOB_NV_RO_BASE),--apob-nv-base) -OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) -OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) -OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) - -OPT_SIGNED_AMDFW_A_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_A_POSITION), --signed-addr) -OPT_SIGNED_AMDFW_A_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_A_FILE), --signed-output) -OPT_SIGNED_AMDFW_B_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_B_POSITION), --signed-addr) -OPT_SIGNED_AMDFW_B_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_B_FILE), --signed-output) - -OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) -OPT_PSP_RO_SOFTFUSE=$(call add_opt_prefix, $(PSP_RO_SOFTFUSE), --soft-fuse) - -OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) -OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) -OPT_SPL_RW_AB_TABLE_FILE=$(call add_opt_prefix, $(SPL_RW_AB_TABLE_FILE), --spl-table) - -# If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant -OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) - -MANIFEST_FILE=$(obj)/amdfw_manifest -OPT_MANIFEST=$(call add_opt_prefix, $(MANIFEST_FILE), --output-manifest) - -AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ - $(OPT_APOB_ADDR) \ - $(OPT_DEBUG_AMDFWTOOL) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - --use-pspsecureos \ - --load-s0i3 \ - $(OPT_TOKEN_UNLOCK) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_PSP_SHAREDMEM_BASE) \ - $(OPT_PSP_SHAREDMEM_SIZE) \ - $(OPT_EFS_SPI_READ_MODE) \ - $(OPT_EFS_SPI_SPEED) \ - $(OPT_EFS_SPI_MICRON_FLAG) \ - --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --flashsize $(CONFIG_ROM_SIZE) \ - $(OPT_RECOVERY_AB_SINGLE_COPY) - -# If vBOOT is not enabled, we want the MP2 firmware in the common AMDFW -ifeq ($(CONFIG_VBOOT),) -AMDFW_COMMON_ARGS += $(OPT_PSP_LOAD_MP2_FW) -OPT_PSP_LOAD_MP2_FW = -else -# Disable MP2 FW loading in VBOOT RO -PSP_RO_SOFTFUSE_BITS += 29 -endif - -$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ - $(PSP_VERSTAGE_FILE) \ - $(PSP_VERSTAGE_SIG_FILE) \ - $$(PSP_APCB_FILES) \ - $(DEP_FILES) \ - $(AMDFWTOOL) \ - $(obj)/fmap_config.h \ - $(objcbfs)/bootblock.elf # this target also creates the .map file - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_RO_SIZE) \ - $(OPT_APOB_NV_RO_BASE) \ - $(OPT_VERSTAGE_FILE) \ - $(OPT_VERSTAGE_SIG_FILE) \ - $(OPT_SPL_TABLE_FILE) \ - $(OPT_MANIFEST) \ - $(OPT_PSP_RO_SOFTFUSE) \ - --location $(CONFIG_AMD_FWM_POSITION) \ - --output $@ - -ifeq ($(CONFIG_CBFS_VERIFICATION)$(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),yy) -$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) - rm -f $@ - $(OBJCOPY_bootblock) -O binary $< $@ -else -$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) - rm -f $@ - @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) -endif - -$(obj)/amdfw_a.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - $(OPT_SPL_RW_AB_TABLE_FILE) \ - $(OPT_SIGNED_AMDFW_A_POSITION) \ - $(OPT_SIGNED_AMDFW_A_FILE) \ - $(OPT_PSP_LOAD_MP2_FW) \ - $(OPT_PSP_SOFTFUSE) \ - --location $(call _tohex,$(MENDOCINO_FW_A_POSITION)) \ - --body-location $(call _tohex,$$(($(MENDOCINO_FW_A_POSITION) + $(MENDOCINO_FW_BODY_OFFSET)))) \ - --anywhere \ - --output $@ - -$(obj)/amdfw_b.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - $(OPT_SPL_RW_AB_TABLE_FILE) \ - $(OPT_SIGNED_AMDFW_B_POSITION) \ - $(OPT_SIGNED_AMDFW_B_FILE) \ - $(OPT_PSP_LOAD_MP2_FW) \ - $(OPT_PSP_SOFTFUSE) \ - --location $(call _tohex,$(MENDOCINO_FW_B_POSITION)) \ - --body-location $(call _tohex,$$(($(MENDOCINO_FW_B_POSITION) + $(MENDOCINO_FW_BODY_OFFSET)))) \ - --anywhere \ - --output $@ - -$(obj)/amdfw_a.rom.body: $(obj)/amdfw_a.rom -$(obj)/amdfw_b.rom.body: $(obj)/amdfw_b.rom - -$(MANIFEST_FILE): $(obj)/amdfw.rom -cbfs-files-y += amdfw_manifest -amdfw_manifest-file := $(MANIFEST_FILE) -amdfw_manifest-type := raw - -ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -cbfs-files-y += apu/amdfw_a -apu/amdfw_a-file := $(obj)/amdfw_a.rom -apu/amdfw_a-position := $(AMD_FW_AB_POSITION) -apu/amdfw_a-type := raw - -cbfs-files-y += apu/amdfw_a_body -apu/amdfw_a_body-file := $(obj)/amdfw_a.rom.body -apu/amdfw_a_body-position := $(call int-add, $(AMD_FW_AB_POSITION) $(MENDOCINO_FW_BODY_OFFSET)) -apu/amdfw_a_body-type := raw -endif - -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -cbfs-files-y += apu/amdfw_b -apu/amdfw_b-file := $(obj)/amdfw_b.rom -apu/amdfw_b-position := $(AMD_FW_AB_POSITION) -apu/amdfw_b-type := raw - -cbfs-files-y += apu/amdfw_b_body -apu/amdfw_b_body-file := $(obj)/amdfw_b.rom.body -apu/amdfw_b_body-position := $(call int-add, $(AMD_FW_AB_POSITION) $(MENDOCINO_FW_BODY_OFFSET)) -apu/amdfw_b_body-type := raw -endif - -ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -build_complete:: $(obj)/amdfw_a.rom.body $(obj)/amdfw_b.rom.body - @printf " Adding Signed ROM and HASH\n" - $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.body.signed - $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.body.signed - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f $(obj)/amdfw_a.rom.body.signed.hash \ - -n apu/amdfw_a_hash -t raw - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.body.signed.hash \ - -n apu/amdfw_b_hash -t raw -endif - -# Add ranges for all components up until the first segment of BIOS to be verified by GSC -ifeq ($(CONFIG_VBOOT_GSCVD),y) -# Adding range for Bootblock -vboot-gscvd-ranges += $(call amdfwread-range-cmd,BIOSL2: 0x62) -# Adding range for PSP Stage1 Bootloader -vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x01) - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# Adding range for PSP Verstage -vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x52) -endif # ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -endif # ifeq ($(CONFIG_VBOOT_GSCVD),y) - -endif # ($(CONFIG_SOC_AMD_MENDOCINO),y) diff --git a/src/soc/amd/mendocino/Makefile.mk b/src/soc/amd/mendocino/Makefile.mk new file mode 100644 index 0000000000..5b9216e638 --- /dev/null +++ b/src/soc/amd/mendocino/Makefile.mk @@ -0,0 +1,366 @@ +# SPDX-License-Identifier: BSD-3-Clause + +ifeq ($(CONFIG_SOC_AMD_MENDOCINO),y) + +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage + +# Beware that all-y also adds the compilation unit to verstage on PSP +all-y += aoac.c +all-y += config.c +all-y += i2c.c + +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + +bootblock-y += early_fch.c +bootblock-y += espi_util.c + +verstage-y += espi_util.c + +romstage-y += fsp_m_params.c + +ramstage-y += acpi.c +ramstage-y += agesa_acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += fch.c +ramstage-y += fsp_misc_data_hob.c +ramstage-y += fsp_s_params.c +ramstage-y += mca.c +ramstage-y += root_complex.c +ramstage-y += xhci.c +ramstage-y += manifest.c + +smm-y += gpio.c +smm-y += smihandler.c +smm-$(CONFIG_DEBUG_SMI) += uart.c + +CPPFLAGS_common += -I$(src)/soc/amd/mendocino/include +CPPFLAGS_common += -I$(src)/soc/amd/mendocino/acpi +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/mendocino +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common + +# Building the cbfs image will fail if the offset, aligned to 64 bytes, isn't large enough +ifeq ($(CONFIG_CBFS_VERIFICATION),y) +# 0x80 accounts for the cbfs_file struct + filename + metadata structs +AMD_FW_AB_POSITION := 0x80 +else # ($(CONFIG_CBFS_VERIFICATION), y) +# 0x40 accounts for the cbfs_file struct + filename + metadata structs without hash attribute +AMD_FW_AB_POSITION := 0x40 +endif # ($(CONFIG_CBFS_VERIFICATION), y) + +MENDOCINO_FW_A_POSITION=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) + +MENDOCINO_FW_B_POSITION=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) + +MENDOCINO_FW_BODY_OFFSET := 0x100 + +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Architecture +# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). +# + +ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) +PSP_SOFTFUSE_BITS += 7 +endif + +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" +endif + +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" +else +# Disable MP2 firmware loading +PSP_SOFTFUSE_BITS += 29 +endif + +# Use additional Soft Fuse bits specified in Kconfig +PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) +PSP_RO_SOFTFUSE_BITS=$(PSP_SOFTFUSE_BITS) + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif + +# type = 0x55 +SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) +ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) +SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) +else +SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) +endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') + +ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) +# type = 0x63 - construct APOB NV base/size from flash map +# The flashmap section used for this is expected to be named RW_MRC_CACHE +APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) + +ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y) +# On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE. +# Else use RW_MRC_CACHE. This entry will be added in the RO section. +APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE) +APOB_NV_RO_BASE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_START) +else +APOB_NV_RO_SIZE=$(APOB_NV_SIZE) +APOB_NV_RO_BASE=$(APOB_NV_BASE) +endif +endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +# type = 0x6B - PSP Shared memory location +ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) +PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) +PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) +endif + +# type = 0x52 - PSP Bootloader Userspace Application (verstage) +PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) +PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) +endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK + +ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) +SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ + $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) \ + $(call get_fmap_value,FMAP_SECTION_FLASH_START)) +SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ + $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) \ + $(call get_fmap_value,FMAP_SECTION_FLASH_START)) +SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.body.signed +SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.body.signed +endif # CONFIG_SEPARATE_SIGNED_PSPFW + +# Helper function to return a value with given bit set +# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) +PSP_RO_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(sort $(PSP_RO_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) +OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) + +OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ + $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ + $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) +OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) +OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) +OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) +OPT_APOB_NV_RO_SIZE=$(call add_opt_prefix, $(APOB_NV_RO_SIZE), --apob-nv-size) +OPT_APOB_NV_RO_BASE=$(call add_opt_prefix, $(APOB_NV_RO_BASE),--apob-nv-base) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) + +OPT_SIGNED_AMDFW_A_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_A_POSITION), --signed-addr) +OPT_SIGNED_AMDFW_A_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_A_FILE), --signed-output) +OPT_SIGNED_AMDFW_B_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_B_POSITION), --signed-addr) +OPT_SIGNED_AMDFW_B_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_B_FILE), --signed-output) + +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) +OPT_PSP_RO_SOFTFUSE=$(call add_opt_prefix, $(PSP_RO_SOFTFUSE), --soft-fuse) + +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) +OPT_SPL_RW_AB_TABLE_FILE=$(call add_opt_prefix, $(SPL_RW_AB_TABLE_FILE), --spl-table) + +# If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant +OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) + +MANIFEST_FILE=$(obj)/amdfw_manifest +OPT_MANIFEST=$(call add_opt_prefix, $(MANIFEST_FILE), --output-manifest) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + $(OPT_DEBUG_AMDFWTOOL) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + --use-pspsecureos \ + --load-s0i3 \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --flashsize $(CONFIG_ROM_SIZE) \ + $(OPT_RECOVERY_AB_SINGLE_COPY) + +# If vBOOT is not enabled, we want the MP2 firmware in the common AMDFW +ifeq ($(CONFIG_VBOOT),) +AMDFW_COMMON_ARGS += $(OPT_PSP_LOAD_MP2_FW) +OPT_PSP_LOAD_MP2_FW = +else +# Disable MP2 FW loading in VBOOT RO +PSP_RO_SOFTFUSE_BITS += 29 +endif + +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $(PSP_VERSTAGE_FILE) \ + $(PSP_VERSTAGE_SIG_FILE) \ + $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ + $(AMDFWTOOL) \ + $(obj)/fmap_config.h \ + $(objcbfs)/bootblock.elf # this target also creates the .map file + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_RO_SIZE) \ + $(OPT_APOB_NV_RO_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ + $(OPT_SPL_TABLE_FILE) \ + $(OPT_MANIFEST) \ + $(OPT_PSP_RO_SOFTFUSE) \ + --location $(CONFIG_AMD_FWM_POSITION) \ + --output $@ + +ifeq ($(CONFIG_CBFS_VERIFICATION)$(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),yy) +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) + rm -f $@ + $(OBJCOPY_bootblock) -O binary $< $@ +else +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) +endif + +$(obj)/amdfw_a.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + $(OPT_SPL_RW_AB_TABLE_FILE) \ + $(OPT_SIGNED_AMDFW_A_POSITION) \ + $(OPT_SIGNED_AMDFW_A_FILE) \ + $(OPT_PSP_LOAD_MP2_FW) \ + $(OPT_PSP_SOFTFUSE) \ + --location $(call _tohex,$(MENDOCINO_FW_A_POSITION)) \ + --body-location $(call _tohex,$$(($(MENDOCINO_FW_A_POSITION) + $(MENDOCINO_FW_BODY_OFFSET)))) \ + --anywhere \ + --output $@ + +$(obj)/amdfw_b.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + $(OPT_SPL_RW_AB_TABLE_FILE) \ + $(OPT_SIGNED_AMDFW_B_POSITION) \ + $(OPT_SIGNED_AMDFW_B_FILE) \ + $(OPT_PSP_LOAD_MP2_FW) \ + $(OPT_PSP_SOFTFUSE) \ + --location $(call _tohex,$(MENDOCINO_FW_B_POSITION)) \ + --body-location $(call _tohex,$$(($(MENDOCINO_FW_B_POSITION) + $(MENDOCINO_FW_BODY_OFFSET)))) \ + --anywhere \ + --output $@ + +$(obj)/amdfw_a.rom.body: $(obj)/amdfw_a.rom +$(obj)/amdfw_b.rom.body: $(obj)/amdfw_b.rom + +$(MANIFEST_FILE): $(obj)/amdfw.rom +cbfs-files-y += amdfw_manifest +amdfw_manifest-file := $(MANIFEST_FILE) +amdfw_manifest-type := raw + +ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_a +apu/amdfw_a-file := $(obj)/amdfw_a.rom +apu/amdfw_a-position := $(AMD_FW_AB_POSITION) +apu/amdfw_a-type := raw + +cbfs-files-y += apu/amdfw_a_body +apu/amdfw_a_body-file := $(obj)/amdfw_a.rom.body +apu/amdfw_a_body-position := $(call int-add, $(AMD_FW_AB_POSITION) $(MENDOCINO_FW_BODY_OFFSET)) +apu/amdfw_a_body-type := raw +endif + +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_b +apu/amdfw_b-file := $(obj)/amdfw_b.rom +apu/amdfw_b-position := $(AMD_FW_AB_POSITION) +apu/amdfw_b-type := raw + +cbfs-files-y += apu/amdfw_b_body +apu/amdfw_b_body-file := $(obj)/amdfw_b.rom.body +apu/amdfw_b_body-position := $(call int-add, $(AMD_FW_AB_POSITION) $(MENDOCINO_FW_BODY_OFFSET)) +apu/amdfw_b_body-type := raw +endif + +ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +build_complete:: $(obj)/amdfw_a.rom.body $(obj)/amdfw_b.rom.body + @printf " Adding Signed ROM and HASH\n" + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.body.signed + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.body.signed + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f $(obj)/amdfw_a.rom.body.signed.hash \ + -n apu/amdfw_a_hash -t raw + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.body.signed.hash \ + -n apu/amdfw_b_hash -t raw +endif + +# Add ranges for all components up until the first segment of BIOS to be verified by GSC +ifeq ($(CONFIG_VBOOT_GSCVD),y) +# Adding range for Bootblock +vboot-gscvd-ranges += $(call amdfwread-range-cmd,BIOSL2: 0x62) +# Adding range for PSP Stage1 Bootloader +vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x01) + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +# Adding range for PSP Verstage +vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x52) +endif # ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +endif # ifeq ($(CONFIG_VBOOT_GSCVD),y) + +endif # ($(CONFIG_SOC_AMD_MENDOCINO),y) diff --git a/src/soc/amd/mendocino/psp_verstage/Makefile.inc b/src/soc/amd/mendocino/psp_verstage/Makefile.inc deleted file mode 100644 index 19dd8a7225..0000000000 --- a/src/soc/amd/mendocino/psp_verstage/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/mendocino/include - -verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include - -subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage - -verstage-y += svc.c -verstage-y += chipset.c -verstage-y += uart.c - -verstage-y += $(top)/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_startup.S -verstage-y += $(top)/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/mendocino/psp_verstage/Makefile.mk b/src/soc/amd/mendocino/psp_verstage/Makefile.mk new file mode 100644 index 0000000000..19dd8a7225 --- /dev/null +++ b/src/soc/amd/mendocino/psp_verstage/Makefile.mk @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/mendocino/include + +verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include + +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage + +verstage-y += svc.c +verstage-y += chipset.c +verstage-y += uart.c + +verstage-y += $(top)/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc deleted file mode 100644 index 82ce54d91e..0000000000 --- a/src/soc/amd/phoenix/Makefile.inc +++ /dev/null @@ -1,357 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -# TODO: Move as much as possible to common -# TODO: Update for Phoenix - -ifeq ($(CONFIG_SOC_AMD_PHOENIX_BASE),y) - -subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage - -# Beware that all-y also adds the compilation unit to verstage on PSP -all-y += aoac.c -all-y += config.c -all-y += i2c.c - -# all_x86-y adds the compilation unit to all stages that run on the x86 cores -all_x86-y += gpio.c -all_x86-y += uart.c - -bootblock-y += early_fch.c -bootblock-y += espi_util.c - -verstage-y += espi_util.c - -romstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_m_params.c -romstage-y += soc_util.c - -ramstage-y += acpi.c -ramstage-y += agesa_acpi.c -ramstage-y += chip.c -ramstage-y += cpu.c -ramstage-y += fch.c -ramstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_s_params.c -ramstage-y += graphics.c -ramstage-y += mca.c -ramstage-y += root_complex.c -ramstage-y += soc_util.c -ramstage-y += xhci.c - -smm-y += gpio.c -smm-y += smihandler.c -smm-$(CONFIG_DEBUG_SMI) += uart.c - -CPPFLAGS_common += -I$(src)/soc/amd/phoenix/include -CPPFLAGS_common += -I$(src)/soc/amd/phoenix/acpi -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/phoenix -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common - -# Building the cbfs image will fail if the offset, aligned to 64 bytes, isn't large enough -ifeq ($(CONFIG_CBFS_VERIFICATION),y) -# 0x80 accounts for the cbfs_file struct + filename + metadata structs -AMD_FW_AB_POSITION := 0x80 -else # ($(CONFIG_CBFS_VERIFICATION), y) -# 0x40 accounts for the cbfs_file struct + filename + metadata structs without hash attribute -AMD_FW_AB_POSITION := 0x40 -endif # ($(CONFIG_CBFS_VERIFICATION), y) - -PHOENIX_FW_A_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) - -PHOENIX_FW_B_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) - -FMAP_FLASH_START=$(call get_fmap_value,FMAP_SECTION_FLASH_START) - -# -# PSP Directory Table items -# -# Certain ordering requirements apply, however these are ensured by amdfwtool. -# For more information see "AMD Platform Security Processor BIOS Architecture -# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). -# - -ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) -PSP_SOFTFUSE_BITS += 7 -endif - -ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) -# Enable secure debug unlock -PSP_SOFTFUSE_BITS += 0 -OPT_TOKEN_UNLOCK="--token-unlock" -endif - -ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) -OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" -else -# Disable MP2 firmware loading -PSP_SOFTFUSE_BITS += 29 -endif - -# Use additional Soft Fuse bits specified in Kconfig -PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) - -# type = 0x3a -ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) -PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) -endif - -# type = 0x55 -SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) -SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) -else -SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -endif - -# -# BIOS Directory Table items - proper ordering is managed by amdfwtool -# - -# type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) - -# type = 0x61 -PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) - -# type = 0x62 -PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img -PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') - -ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) -# type = 0x63 - construct APOB NV base/size from flash map -# The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) -APOB_NV_BASE=$(call _tohex,$(call int-subtract, \ - $(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) $(FMAP_FLASH_START))) - -ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y) -# On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE. -# Else use RW_MRC_CACHE. This entry will be added in the RO section. -APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE) -APOB_NV_RO_BASE=$(call _tohex,$(call int-subtract, \ - $(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_START) $(FMAP_FLASH_START))) -else -APOB_NV_RO_SIZE=$(APOB_NV_SIZE) -APOB_NV_RO_BASE=$(APOB_NV_BASE) -endif -endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE - -ifeq ($(CONFIG_AMDFW_SPLIT),y) -FMAP_AMDFW_BODY_LOCATION=$(call get_fmap_value,FMAP_SECTION_AMDFWBODY_START) -endif - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# type = 0x6B - PSP Shared memory location -ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) -PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) -PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) -endif - -# type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) -PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) -endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK - -ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) -SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ - $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) $(FMAP_FLASH_START)) -SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ - $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) $(FMAP_FLASH_START)) -SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed -SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed -endif # CONFIG_SEPARATE_SIGNED_PSPFW - -# Helper function to return a value with given bit set -# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. -set-bit=$(call int-shift-left, 1 $(call _toint,$1)) -PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) - -# -# Build the arguments to amdfwtool (order is unimportant). Missing file names -# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. -# - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) -OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) - -OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ - $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ - $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) - -OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) -OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) -OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) -OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) - -OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) -OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) -OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) -OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) -OPT_APOB_NV_RO_SIZE=$(call add_opt_prefix, $(APOB_NV_RO_SIZE), --apob-nv-size) -OPT_APOB_NV_RO_BASE=$(call add_opt_prefix, $(APOB_NV_RO_BASE),--apob-nv-base) -OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) -OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) -OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) - -OPT_SIGNED_AMDFW_A_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_A_POSITION), --signed-addr) -OPT_SIGNED_AMDFW_A_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_A_FILE), --signed-output) -OPT_SIGNED_AMDFW_B_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_B_POSITION), --signed-addr) -OPT_SIGNED_AMDFW_B_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_B_FILE), --signed-output) - -OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) - -OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) -OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) -OPT_SPL_RW_AB_TABLE_FILE=$(call add_opt_prefix, $(SPL_RW_AB_TABLE_FILE), --spl-table) - -# If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant -OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) - -OPT_AMDFW_BODY_LOCATION=$(call add_opt_prefix, $(FMAP_AMDFW_BODY_LOCATION), --body-location) - -MANIFEST_FILE=$(obj)/amdfw_manifest -OPT_MANIFEST=$(call add_opt_prefix, $(MANIFEST_FILE), --output-manifest) - -AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ - $(OPT_APOB_ADDR) \ - $(OPT_DEBUG_AMDFWTOOL) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_LOAD_MP2_FW) \ - --use-pspsecureos \ - --load-s0i3 \ - $(OPT_TOKEN_UNLOCK) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_PSP_SHAREDMEM_BASE) \ - $(OPT_PSP_SHAREDMEM_SIZE) \ - $(OPT_EFS_SPI_READ_MODE) \ - $(OPT_EFS_SPI_SPEED) \ - $(OPT_EFS_SPI_MICRON_FLAG) \ - --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --flashsize $(CONFIG_ROM_SIZE) \ - $(OPT_RECOVERY_AB_SINGLE_COPY) \ - $(OPT_AMDFW_BODY_LOCATION) - -$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ - $(PSP_VERSTAGE_FILE) \ - $(PSP_VERSTAGE_SIG_FILE) \ - $$(PSP_APCB_FILES) \ - $(DEP_FILES) \ - $(AMDFWTOOL) \ - $(obj)/fmap_config.h \ - $(objcbfs)/bootblock.elf # this target also creates the .map file - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_RO_SIZE) \ - $(OPT_APOB_NV_RO_BASE) \ - $(OPT_VERSTAGE_FILE) \ - $(OPT_VERSTAGE_SIG_FILE) \ - $(OPT_SPL_TABLE_FILE) \ - $(OPT_MANIFEST) \ - --location $(CONFIG_AMD_FWM_POSITION) \ - --output $@ - -ifeq ($(CONFIG_AMDFW_SPLIT),y) -$(obj)/amdfw.rom.body: $(obj)/amdfw.rom -$(call add_intermediate, add_amdfwbody, $(obj)/amdfw.rom.body) - $(CBFSTOOL) $(obj)/coreboot.pre write -r AMDFWBODY -f $(obj)/amdfw.rom.body --fill-upward -endif - -$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) - rm -f $@ - @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) - -$(obj)/amdfw_a.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - $(OPT_SPL_RW_AB_TABLE_FILE) \ - $(OPT_SIGNED_AMDFW_A_POSITION) \ - $(OPT_SIGNED_AMDFW_A_FILE) \ - --location $(call _tohex,$(PHOENIX_FW_A_POSITION)) \ - --anywhere \ - --output $@ - -$(obj)/amdfw_b.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - $(OPT_SPL_RW_AB_TABLE_FILE) \ - $(OPT_SIGNED_AMDFW_B_POSITION) \ - $(OPT_SIGNED_AMDFW_B_FILE) \ - --location $(call _tohex,$(PHOENIX_FW_B_POSITION)) \ - --anywhere \ - --output $@ - - -$(MANIFEST_FILE): $(obj)/amdfw.rom -cbfs-files-y += amdfw_manifest -amdfw_manifest-file := $(MANIFEST_FILE) -amdfw_manifest-type := raw - -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -cbfs-files-y += apu/amdfw_a -apu/amdfw_a-file := $(obj)/amdfw_a.rom -apu/amdfw_a-position := $(AMD_FW_AB_POSITION) -apu/amdfw_a-type := raw - -cbfs-files-y += apu/amdfw_b -apu/amdfw_b-file := $(obj)/amdfw_b.rom -apu/amdfw_b-position := $(AMD_FW_AB_POSITION) -apu/amdfw_b-type := raw - -ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) -build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom - @printf " Adding Signed ROM and HASH\n" - $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed - $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.signed - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f $(obj)/amdfw_a.rom.signed.hash \ - -n apu/amdfw_a_hash -t raw - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.signed.hash \ - -n apu/amdfw_b_hash -t raw - if [ -n "$(wildcard $(obj)/amdfw_a.rom.signed.1.hash)" ]; then \ - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f \ - $(obj)/amdfw_a.rom.signed.1.hash -n apu/amdfw_a_hash1 -t raw; \ - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f \ - $(obj)/amdfw_b.rom.signed.1.hash -n apu/amdfw_b_hash1 -t raw; \ - fi - if [ -n "$(wildcard $(obj)/amdfw_a.rom.signed.2.hash)" ]; then \ - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f \ - $(obj)/amdfw_a.rom.signed.2.hash -n apu/amdfw_a_hash2 -t raw; \ - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f \ - $(obj)/amdfw_b.rom.signed.2.hash -n apu/amdfw_b_hash2 -t raw; \ - fi -endif # CONFIG_SEPARATE_SIGNED_PSPFW -endif - -# Add ranges for all components up until the first segment of BIOS to be verified by GSC -ifeq ($(CONFIG_VBOOT_GSCVD),y) -# Adding range for Bootblock -vboot-gscvd-ranges += $(call amdfwread-range-cmd,BIOSL2: 0x62) -# Adding range for PSP Stage1 Bootloader -vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x01) - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# Adding range for PSP Verstage -vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x52) -endif # ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -endif # ifeq ($(CONFIG_VBOOT_GSCVD),y) - -endif # ($(CONFIG_SOC_AMD_PHOENIX_BASE),y) diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk new file mode 100644 index 0000000000..82ce54d91e --- /dev/null +++ b/src/soc/amd/phoenix/Makefile.mk @@ -0,0 +1,357 @@ +# SPDX-License-Identifier: BSD-3-Clause + +# TODO: Move as much as possible to common +# TODO: Update for Phoenix + +ifeq ($(CONFIG_SOC_AMD_PHOENIX_BASE),y) + +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage + +# Beware that all-y also adds the compilation unit to verstage on PSP +all-y += aoac.c +all-y += config.c +all-y += i2c.c + +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + +bootblock-y += early_fch.c +bootblock-y += espi_util.c + +verstage-y += espi_util.c + +romstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_m_params.c +romstage-y += soc_util.c + +ramstage-y += acpi.c +ramstage-y += agesa_acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += fch.c +ramstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_s_params.c +ramstage-y += graphics.c +ramstage-y += mca.c +ramstage-y += root_complex.c +ramstage-y += soc_util.c +ramstage-y += xhci.c + +smm-y += gpio.c +smm-y += smihandler.c +smm-$(CONFIG_DEBUG_SMI) += uart.c + +CPPFLAGS_common += -I$(src)/soc/amd/phoenix/include +CPPFLAGS_common += -I$(src)/soc/amd/phoenix/acpi +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/phoenix +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common + +# Building the cbfs image will fail if the offset, aligned to 64 bytes, isn't large enough +ifeq ($(CONFIG_CBFS_VERIFICATION),y) +# 0x80 accounts for the cbfs_file struct + filename + metadata structs +AMD_FW_AB_POSITION := 0x80 +else # ($(CONFIG_CBFS_VERIFICATION), y) +# 0x40 accounts for the cbfs_file struct + filename + metadata structs without hash attribute +AMD_FW_AB_POSITION := 0x40 +endif # ($(CONFIG_CBFS_VERIFICATION), y) + +PHOENIX_FW_A_POSITION=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) + +PHOENIX_FW_B_POSITION=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) + +FMAP_FLASH_START=$(call get_fmap_value,FMAP_SECTION_FLASH_START) + +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Architecture +# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). +# + +ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) +PSP_SOFTFUSE_BITS += 7 +endif + +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" +endif + +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" +else +# Disable MP2 firmware loading +PSP_SOFTFUSE_BITS += 29 +endif + +# Use additional Soft Fuse bits specified in Kconfig +PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif + +# type = 0x55 +SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) +ifeq ($(CONFIG_HAVE_SPL_RW_AB_FILE),y) +SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_RW_AB_TABLE_FILE) +else +SPL_RW_AB_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) +endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') + +ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) +# type = 0x63 - construct APOB NV base/size from flash map +# The flashmap section used for this is expected to be named RW_MRC_CACHE +APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call _tohex,$(call int-subtract, \ + $(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) $(FMAP_FLASH_START))) + +ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y) +# On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE. +# Else use RW_MRC_CACHE. This entry will be added in the RO section. +APOB_NV_RO_SIZE=$(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE) +APOB_NV_RO_BASE=$(call _tohex,$(call int-subtract, \ + $(call get_fmap_value,FMAP_SECTION_RECOVERY_MRC_CACHE_START) $(FMAP_FLASH_START))) +else +APOB_NV_RO_SIZE=$(APOB_NV_SIZE) +APOB_NV_RO_BASE=$(APOB_NV_BASE) +endif +endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE + +ifeq ($(CONFIG_AMDFW_SPLIT),y) +FMAP_AMDFW_BODY_LOCATION=$(call get_fmap_value,FMAP_SECTION_AMDFWBODY_START) +endif + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +# type = 0x6B - PSP Shared memory location +ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) +PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) +PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) +endif + +# type = 0x52 - PSP Bootloader Userspace Application (verstage) +PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) +PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) +endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK + +ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) +SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ + $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_A_START) $(FMAP_FLASH_START)) +SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ + $(call get_fmap_value,FMAP_SECTION_SIGNED_AMDFW_B_START) $(FMAP_FLASH_START)) +SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed +SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed +endif # CONFIG_SEPARATE_SIGNED_PSPFW + +# Helper function to return a value with given bit set +# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) +OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) + +OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ + $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ + $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) +OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) +OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) +OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) +OPT_APOB_NV_RO_SIZE=$(call add_opt_prefix, $(APOB_NV_RO_SIZE), --apob-nv-size) +OPT_APOB_NV_RO_BASE=$(call add_opt_prefix, $(APOB_NV_RO_BASE),--apob-nv-base) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) + +OPT_SIGNED_AMDFW_A_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_A_POSITION), --signed-addr) +OPT_SIGNED_AMDFW_A_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_A_FILE), --signed-output) +OPT_SIGNED_AMDFW_B_POSITION=$(call add_opt_prefix, $(SIGNED_AMDFW_B_POSITION), --signed-addr) +OPT_SIGNED_AMDFW_B_FILE=$(call add_opt_prefix, $(SIGNED_AMDFW_B_FILE), --signed-output) + +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) +OPT_SPL_RW_AB_TABLE_FILE=$(call add_opt_prefix, $(SPL_RW_AB_TABLE_FILE), --spl-table) + +# If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant +OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) + +OPT_AMDFW_BODY_LOCATION=$(call add_opt_prefix, $(FMAP_AMDFW_BODY_LOCATION), --body-location) + +MANIFEST_FILE=$(obj)/amdfw_manifest +OPT_MANIFEST=$(call add_opt_prefix, $(MANIFEST_FILE), --output-manifest) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + $(OPT_DEBUG_AMDFWTOOL) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + $(OPT_PSP_LOAD_MP2_FW) \ + --use-pspsecureos \ + --load-s0i3 \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --flashsize $(CONFIG_ROM_SIZE) \ + $(OPT_RECOVERY_AB_SINGLE_COPY) \ + $(OPT_AMDFW_BODY_LOCATION) + +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $(PSP_VERSTAGE_FILE) \ + $(PSP_VERSTAGE_SIG_FILE) \ + $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ + $(AMDFWTOOL) \ + $(obj)/fmap_config.h \ + $(objcbfs)/bootblock.elf # this target also creates the .map file + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_RO_SIZE) \ + $(OPT_APOB_NV_RO_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ + $(OPT_SPL_TABLE_FILE) \ + $(OPT_MANIFEST) \ + --location $(CONFIG_AMD_FWM_POSITION) \ + --output $@ + +ifeq ($(CONFIG_AMDFW_SPLIT),y) +$(obj)/amdfw.rom.body: $(obj)/amdfw.rom +$(call add_intermediate, add_amdfwbody, $(obj)/amdfw.rom.body) + $(CBFSTOOL) $(obj)/coreboot.pre write -r AMDFWBODY -f $(obj)/amdfw.rom.body --fill-upward +endif + +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + +$(obj)/amdfw_a.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + $(OPT_SPL_RW_AB_TABLE_FILE) \ + $(OPT_SIGNED_AMDFW_A_POSITION) \ + $(OPT_SIGNED_AMDFW_A_FILE) \ + --location $(call _tohex,$(PHOENIX_FW_A_POSITION)) \ + --anywhere \ + --output $@ + +$(obj)/amdfw_b.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + $(OPT_SPL_RW_AB_TABLE_FILE) \ + $(OPT_SIGNED_AMDFW_B_POSITION) \ + $(OPT_SIGNED_AMDFW_B_FILE) \ + --location $(call _tohex,$(PHOENIX_FW_B_POSITION)) \ + --anywhere \ + --output $@ + + +$(MANIFEST_FILE): $(obj)/amdfw.rom +cbfs-files-y += amdfw_manifest +amdfw_manifest-file := $(MANIFEST_FILE) +amdfw_manifest-type := raw + +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_a +apu/amdfw_a-file := $(obj)/amdfw_a.rom +apu/amdfw_a-position := $(AMD_FW_AB_POSITION) +apu/amdfw_a-type := raw + +cbfs-files-y += apu/amdfw_b +apu/amdfw_b-file := $(obj)/amdfw_b.rom +apu/amdfw_b-position := $(AMD_FW_AB_POSITION) +apu/amdfw_b-type := raw + +ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) +build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom + @printf " Adding Signed ROM and HASH\n" + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.signed + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f $(obj)/amdfw_a.rom.signed.hash \ + -n apu/amdfw_a_hash -t raw + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.signed.hash \ + -n apu/amdfw_b_hash -t raw + if [ -n "$(wildcard $(obj)/amdfw_a.rom.signed.1.hash)" ]; then \ + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f \ + $(obj)/amdfw_a.rom.signed.1.hash -n apu/amdfw_a_hash1 -t raw; \ + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f \ + $(obj)/amdfw_b.rom.signed.1.hash -n apu/amdfw_b_hash1 -t raw; \ + fi + if [ -n "$(wildcard $(obj)/amdfw_a.rom.signed.2.hash)" ]; then \ + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f \ + $(obj)/amdfw_a.rom.signed.2.hash -n apu/amdfw_a_hash2 -t raw; \ + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f \ + $(obj)/amdfw_b.rom.signed.2.hash -n apu/amdfw_b_hash2 -t raw; \ + fi +endif # CONFIG_SEPARATE_SIGNED_PSPFW +endif + +# Add ranges for all components up until the first segment of BIOS to be verified by GSC +ifeq ($(CONFIG_VBOOT_GSCVD),y) +# Adding range for Bootblock +vboot-gscvd-ranges += $(call amdfwread-range-cmd,BIOSL2: 0x62) +# Adding range for PSP Stage1 Bootloader +vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x01) + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +# Adding range for PSP Verstage +vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x52) +endif # ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +endif # ifeq ($(CONFIG_VBOOT_GSCVD),y) + +endif # ($(CONFIG_SOC_AMD_PHOENIX_BASE),y) diff --git a/src/soc/amd/phoenix/psp_verstage/Makefile.inc b/src/soc/amd/phoenix/psp_verstage/Makefile.inc deleted file mode 100644 index 6a2eaced17..0000000000 --- a/src/soc/amd/phoenix/psp_verstage/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage - -verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include -verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/phoenix/include -verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/common/include - -verstage-y += svc.c -verstage-y += chipset.c -verstage-y += uart.c - -verstage-y +=$(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S -verstage-y += $(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/phoenix/psp_verstage/Makefile.mk b/src/soc/amd/phoenix/psp_verstage/Makefile.mk new file mode 100644 index 0000000000..6a2eaced17 --- /dev/null +++ b/src/soc/amd/phoenix/psp_verstage/Makefile.mk @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage + +verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include +verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/phoenix/include +verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/common/include + +verstage-y += svc.c +verstage-y += chipset.c +verstage-y += uart.c + +verstage-y +=$(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc deleted file mode 100644 index ba58c9178b..0000000000 --- a/src/soc/amd/picasso/Makefile.inc +++ /dev/null @@ -1,271 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -ifeq ($(CONFIG_SOC_AMD_PICASSO),y) - -subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage -subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage - -# Beware that all-y also adds the compilation unit to verstage on PSP -all-y += aoac.c -all-y += config.c -all-y += i2c.c - -# all_x86-y adds the compilation unit to all stages that run on the x86 cores -all_x86-y += gpio.c -all_x86-y += uart.c - -bootblock-y += early_fch.c - -romstage-y += fsp_m_params.c - -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c -ramstage-y += chip.c -ramstage-y += cpu.c -ramstage-y += fch.c -ramstage-y += fsp_s_params.c -ramstage-y += graphics.c -ramstage-y += mca.c -ramstage-y += pcie_gpp.c -ramstage-y += root_complex.c -ramstage-y += sata.c -ramstage-y += soc_util.c -ramstage-y += xhci.c - -smm-y += smihandler.c -ifeq ($(CONFIG_DEBUG_SMI),y) -smm-y += uart.c -endif -smm-y += gpio.c - -CPPFLAGS_common += -I$(src)/soc/amd/picasso/include -CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso/include -CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common - -# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes -# Building the cbfs image will fail if the offset isn't large enough -AMD_FW_AB_POSITION := 0x40 - -PICASSO_FW_A_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) - -PICASSO_FW_B_POSITION=$(call int-add, \ - $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) - -# -# PSP Directory Table items -# -# Certain ordering requirements apply, however these are ensured by amdfwtool. -# For more information see "AMD Platform Security Processor BIOS Architecture -# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). -# - -ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) -# Enable secure debug unlock -PSP_SOFTFUSE_BITS += 0 -OPT_TOKEN_UNLOCK="--token-unlock" -endif - -ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) -OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" -else -# Disable MP2 firmware loading -PSP_SOFTFUSE_BITS += 29 -endif - -# Use additional Soft Fuse bits specified in Kconfig -PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) - -ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) -OPT_PSP_LOAD_S0I3_FW="--load-s0i3" -endif - -# type = 0x3a -ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) -PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) -endif -# -# BIOS Directory Table items - proper ordering is managed by amdfwtool -# - -# type = 0x4 -# The flashmap section used for this is expected to be named PSP_NVRAM -PSP_NVRAM_BASE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_START) -PSP_NVRAM_SIZE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_SIZE) - -# type = 0x7 -# RSA 2048 signature -#ifeq ($(CONFIG_PSP_PLATFORM_SECURE_BOOT),y) -PSP_BIOS_SIG_SIZE=0x100 -#endif - -# type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) - -# type = 0x61 -PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) - -# type = 0x62 -PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img -PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') - -ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) -# type = 0x63 - construct APOB NV base/size from flash map -# The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) -APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) -endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# type = 0x6B - PSP Shared memory location -ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) -PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) -PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) -endif - -# type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) -PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) -endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK - - -# Helper function to return a value with given bit set -# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. -set-bit=$(call int-shift-left, 1 $(call _toint,$1)) -PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) - -# -# Build the arguments to amdfwtool (order is unimportant). Missing file names -# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. -# - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_PSP_NVRAM_BASE=$(call add_opt_prefix, $(PSP_NVRAM_BASE), --nvram-base) -OPT_PSP_NVRAM_SIZE=$(call add_opt_prefix, $(PSP_NVRAM_SIZE), --nvram-size) - -OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) -OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) - -OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ - $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ - --instance $(shell printf "%x" $$(($(i)-1))) --apcb ) ) -OPT_PSP_APCB_FILES_BK=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ - $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ - --instance $(shell printf "1%x" $$(($(i)-1))) --apcb ) ) - -OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) -OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) -OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) -OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) - -OPT_PSP_BIOS_SIG_SIZE=$(call add_opt_prefix, $(PSP_BIOS_SIG_SIZE), --bios-sig-size) -OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) -OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) -OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) -OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) -OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) -OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) -OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) - -OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) - -ifeq ($(CONFIG_VBOOT),) -OPT_APOB0_NV_SIZE=$(OPT_APOB_NV_SIZE) -OPT_APOB0_NV_BASE=$(OPT_APOB_NV_BASE) -endif - -OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) - -AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ - $(OPT_PSP_NVRAM_BASE) \ - $(OPT_PSP_NVRAM_SIZE) \ - $(OPT_PSP_APCB_FILES_BK) \ - $(OPT_APOB_ADDR) \ - $(OPT_DEBUG_AMDFWTOOL) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - $(OPT_PSP_BIOS_SIG_SIZE) \ - $(OPT_PSP_SOFTFUSE) \ - --use-pspsecureos \ - $(OPT_PSP_LOAD_MP2_FW) \ - $(OPT_PSP_LOAD_S0I3_FW) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_PSP_SHAREDMEM_BASE) \ - $(OPT_PSP_SHAREDMEM_SIZE) \ - $(OPT_TOKEN_UNLOCK) \ - $(OPT_EFS_SPI_READ_MODE) \ - $(OPT_EFS_SPI_SPEED) \ - $(OPT_EFS_SPI_MICRON_FLAG) \ - --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --flashsize $(CONFIG_ROM_SIZE) - -$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ - $(PSP_VERSTAGE_FILE) \ - $(PSP_VERSTAGE_SIG_FILE) \ - $$(PSP_APCB_FILES) \ - $(DEP_FILES) \ - $(AMDFWTOOL) \ - $(obj)/fmap_config.h \ - $(objcbfs)/bootblock.elf # this target also creates the .map file - $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB0_NV_SIZE) \ - $(OPT_APOB0_NV_BASE) \ - $(OPT_VERSTAGE_FILE) \ - $(OPT_VERSTAGE_SIG_FILE) \ - --location $(CONFIG_AMD_FWM_POSITION) \ - --output $@ - -$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) - rm -f $@ - @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ - --maxsize $(PSP_BIOSBIN_SIZE) - -$(obj)/amdfw_a.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - --location $(call _tohex,$(PICASSO_FW_A_POSITION)) \ - --anywhere \ - --output $@ - -$(obj)/amdfw_b.rom: $(obj)/amdfw.rom - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ - --location $(call _tohex,$(PICASSO_FW_B_POSITION)) \ - --anywhere \ - --output $@ - -ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -cbfs-files-y += apu/amdfw_a -apu/amdfw_a-file := $(obj)/amdfw_a.rom -apu/amdfw_a-position := $(AMD_FW_AB_POSITION) -apu/amdfw_a-type := raw -endif - -ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -cbfs-files-y += apu/amdfw_b -apu/amdfw_b-file := $(obj)/amdfw_b.rom -apu/amdfw_b-position := $(AMD_FW_AB_POSITION) -apu/amdfw_b-type := raw -endif - -endif # ($(CONFIG_SOC_AMD_PICASSO),y) diff --git a/src/soc/amd/picasso/Makefile.mk b/src/soc/amd/picasso/Makefile.mk new file mode 100644 index 0000000000..ba58c9178b --- /dev/null +++ b/src/soc/amd/picasso/Makefile.mk @@ -0,0 +1,271 @@ +# SPDX-License-Identifier: BSD-3-Clause + +ifeq ($(CONFIG_SOC_AMD_PICASSO),y) + +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage + +# Beware that all-y also adds the compilation unit to verstage on PSP +all-y += aoac.c +all-y += config.c +all-y += i2c.c + +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + +bootblock-y += early_fch.c + +romstage-y += fsp_m_params.c + +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += fch.c +ramstage-y += fsp_s_params.c +ramstage-y += graphics.c +ramstage-y += mca.c +ramstage-y += pcie_gpp.c +ramstage-y += root_complex.c +ramstage-y += sata.c +ramstage-y += soc_util.c +ramstage-y += xhci.c + +smm-y += smihandler.c +ifeq ($(CONFIG_DEBUG_SMI),y) +smm-y += uart.c +endif +smm-y += gpio.c + +CPPFLAGS_common += -I$(src)/soc/amd/picasso/include +CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso/include +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common + +# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes +# Building the cbfs image will fail if the offset isn't large enough +AMD_FW_AB_POSITION := 0x40 + +PICASSO_FW_A_POSITION=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) + +PICASSO_FW_B_POSITION=$(call int-add, \ + $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) + +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Architecture +# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). +# + +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" +endif + +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" +else +# Disable MP2 firmware loading +PSP_SOFTFUSE_BITS += 29 +endif + +# Use additional Soft Fuse bits specified in Kconfig +PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) + +ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) +OPT_PSP_LOAD_S0I3_FW="--load-s0i3" +endif + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x4 +# The flashmap section used for this is expected to be named PSP_NVRAM +PSP_NVRAM_BASE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_START) +PSP_NVRAM_SIZE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_SIZE) + +# type = 0x7 +# RSA 2048 signature +#ifeq ($(CONFIG_PSP_PLATFORM_SECURE_BOOT),y) +PSP_BIOS_SIG_SIZE=0x100 +#endif + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') + +ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) +# type = 0x63 - construct APOB NV base/size from flash map +# The flashmap section used for this is expected to be named RW_MRC_CACHE +APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) +endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +# type = 0x6B - PSP Shared memory location +ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) +PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) +PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) +endif + +# type = 0x52 - PSP Bootloader Userspace Application (verstage) +PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) +PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) +endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK + + +# Helper function to return a value with given bit set +# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_PSP_NVRAM_BASE=$(call add_opt_prefix, $(PSP_NVRAM_BASE), --nvram-base) +OPT_PSP_NVRAM_SIZE=$(call add_opt_prefix, $(PSP_NVRAM_SIZE), --nvram-size) + +OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) +OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) + +OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ + $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ + --instance $(shell printf "%x" $$(($(i)-1))) --apcb ) ) +OPT_PSP_APCB_FILES_BK=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ + $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ + --instance $(shell printf "1%x" $$(($(i)-1))) --apcb ) ) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_PSP_BIOS_SIG_SIZE=$(call add_opt_prefix, $(PSP_BIOS_SIG_SIZE), --bios-sig-size) +OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) +OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) +OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) +OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) + +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + +ifeq ($(CONFIG_VBOOT),) +OPT_APOB0_NV_SIZE=$(OPT_APOB_NV_SIZE) +OPT_APOB0_NV_BASE=$(OPT_APOB_NV_BASE) +endif + +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_PSP_NVRAM_BASE) \ + $(OPT_PSP_NVRAM_SIZE) \ + $(OPT_PSP_APCB_FILES_BK) \ + $(OPT_APOB_ADDR) \ + $(OPT_DEBUG_AMDFWTOOL) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_BIOS_SIG_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + --use-pspsecureos \ + $(OPT_PSP_LOAD_MP2_FW) \ + $(OPT_PSP_LOAD_S0I3_FW) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --flashsize $(CONFIG_ROM_SIZE) + +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $(PSP_VERSTAGE_FILE) \ + $(PSP_VERSTAGE_SIG_FILE) \ + $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ + $(AMDFWTOOL) \ + $(obj)/fmap_config.h \ + $(objcbfs)/bootblock.elf # this target also creates the .map file + $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB0_NV_SIZE) \ + $(OPT_APOB0_NV_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ + --location $(CONFIG_AMD_FWM_POSITION) \ + --output $@ + +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + +$(obj)/amdfw_a.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + --location $(call _tohex,$(PICASSO_FW_A_POSITION)) \ + --anywhere \ + --output $@ + +$(obj)/amdfw_b.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + --location $(call _tohex,$(PICASSO_FW_B_POSITION)) \ + --anywhere \ + --output $@ + +ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_a +apu/amdfw_a-file := $(obj)/amdfw_a.rom +apu/amdfw_a-position := $(AMD_FW_AB_POSITION) +apu/amdfw_a-type := raw +endif + +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_b +apu/amdfw_b-file := $(obj)/amdfw_b.rom +apu/amdfw_b-position := $(AMD_FW_AB_POSITION) +apu/amdfw_b-type := raw +endif + +endif # ($(CONFIG_SOC_AMD_PICASSO),y) diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc deleted file mode 100644 index bf1a69448d..0000000000 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include - -verstage-y += svc.c -verstage-y += chipset.c -verstage-y += uart.c - -verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S -verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.mk b/src/soc/amd/picasso/psp_verstage/Makefile.mk new file mode 100644 index 0000000000..bf1a69448d --- /dev/null +++ b/src/soc/amd/picasso/psp_verstage/Makefile.mk @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include + +verstage-y += svc.c +verstage-y += chipset.c +verstage-y += uart.c + +verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc deleted file mode 100644 index c1c74ea2ea..0000000000 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ /dev/null @@ -1,192 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) - -subdirs-y += ../../../cpu/amd/mtrr/ - -bootblock-y += aoac.c -bootblock-y += BiosCallOuts.c -bootblock-y += bootblock.c -bootblock-y += early_fch.c -bootblock-y += gpio.c -bootblock-y += i2c.c -bootblock-y += enable_usbdebug.c - -romstage-y += BiosCallOuts.c -romstage-y += i2c.c -romstage-y += romstage.c -romstage-y += enable_usbdebug.c -romstage-y += fch_agesa.c -romstage-y += gpio.c -romstage-y += smbus_spd.c -romstage-y += memmap.c -romstage-y += psp.c - -verstage-y += gpio.c -verstage-y += i2c.c - -postcar-y += memmap.c -postcar-$(CONFIG_TPM_MEASURED_BOOT) += i2c.c - -ramstage-y += aoac.c -ramstage-y += BiosCallOuts.c -ramstage-y += i2c.c -ramstage-y += chip.c -ramstage-y += cpu.c -ramstage-y += mca.c -ramstage-y += enable_usbdebug.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-y += fch.c -ramstage-y += fch_agesa.c -ramstage-y += gpio.c -ramstage-y += graphics.c -ramstage-y += northbridge.c -ramstage-y += sata.c -ramstage-y += memmap.c -ramstage-y += usb.c -ramstage-y += psp.c - -all-y += monotonic_timer.c -all-y += pstate_util.c -all-y += reset.c -all-y += tsc_freq.c -all-y += uart.c - -smm-y += pstate_util.c -smm-y += monotonic_timer.c -smm-y += smihandler.c -smm-y += tsc_freq.c -smm-$(CONFIG_DEBUG_SMI) += uart.c -smm-y += gpio.c -smm-y += psp.c - -CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include -CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/acpi - -# ROMSIG Normally At ROMBASE + 0x20000 -# +-----------+---------------+----------------+------------+ -# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | -# +-----------+---------------+----------------+------------+ -# |PSPDIR ADDR| -# +-----------+ -# -# EC ROM should be 64K aligned. -### 0 - -FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') - -ifneq ($(FIRMWARE_LOCATION),) - -ifeq ($(CONFIG_AMD_APU_STONEYRIDGE),y) -FIRMWARE_TYPE=ST -else -ifeq ($(CONFIG_AMD_APU_MERLINFALCON),y) -FIRMWARE_TYPE=CZ -else -ifeq ($(CONFIG_AMD_APU_PRAIRIEFALCON),y) -FIRMWARE_TYPE=ST -else -$(error soc/amd/stoneyridge: Unusable FIRMWARE_TYPE) - -endif # CONFIG_AMD_APU_PRAIRIEFALCON -endif # CONFIG_AMD_APU_MERLINFALCON -endif # CONFIG_AMD_APU_STONEYRIDGE - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) -OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE), --gec) - -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATION)/$(shell awk '($$1=="PSP_SMUFW1_SUB0_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATION)/$(shell awk '($$1=="PSP_SMUFW1_SUB1_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) - -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATION)/$(shell awk '($$1=="PSP_SMUFW2_SUB0_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) -SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATION)/$(shell awk '($$1=="PSP_SMUFW2_SUB1_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) - -ifeq ("$(wildcard $(SMUFWM_FN_FILE))","") -SMUFWM_FN_FILE= -SMUFIRMWARE2_FN_FILE= -endif - -ifeq ($(CONFIG_USE_PSPSECUREOS),y) -PSP_USE_PSPSECUREOS="--use-pspsecureos" -endif - -OPT_PSP_USE_PSPSECUREOS=$(call strip_quotes, $(PSP_USE_PSPSECUREOS)) - -OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) -OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) - -$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ - $(DEP_FILES) \ - $(AMDFWTOOL) - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(OPT_STONEYRIDGE_XHCI_FWM_FILE) \ - $(OPT_STONEYRIDGE_GEC_FWM_FILE) \ - $(OPT_PSP_USE_PSPSECUREOS) \ - $(OPT_EFS_SPI_READ_MODE) \ - $(OPT_EFS_SPI_SPEED) \ - $(OPT_DEBUG_AMDFWTOOL) \ - --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --flashsize $(CONFIG_ROM_SIZE) \ - --location $(CONFIG_AMD_FWM_POSITION) \ - --output $@ - -ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) - -$(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) - printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ - "$(CONFIG_AMD_FWM_POSITION)" - dd if=$(obj)/amdfw.rom \ - of=$< conv=notrunc bs=1 \ - seek=$(CONFIG_AMD_FWM_POSITION) >/dev/null 2>&1 - -else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) - -STONEYRIDGE_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) \ - 1 \ - $(CONFIG_AMD_FWM_POSITION)) -cbfs-files-y += apu/amdfw -apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION) -apu/amdfw-type := raw - -endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) - -ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) - -cbfs-files-y += smu_fw -cbfs-files-y += smu_fw2 -smu_fw-type := raw -smu_fw2-type := raw - -ifeq ($(CONFIG_SOC_AMD_SMU_FANLESS),y) -smu_fw-file := $(SMUFWM_FN_FILE) -smu_fw2-file := $(SMUFIRMWARE2_FN_FILE) -else ifeq ($(CONFIG_SOC_AMD_SMU_FANNED),y) -smu_fw-file := $(SMUFWM_FILE) -smu_fw2-file := $(SMUFIRMWARE2_FILE) -else -$(error "Proper SMU Firmware not selected") -endif - -endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) - -else # ifneq ($(FIRMWARE_LOCATION),) - -warn_no_amdfw: - printf "\n\t** WARNING **\n" - printf "coreboot has been built with no PSP firmware and " - printf "a non-booting image has been generated.\n\n" - -PHONY+=warn_no_amdfw - -show_notices:: warn_no_amdfw - -endif # ifneq ($(FIRMWARE_LOCATION),) - -endif # ($(CONFIG_SOC_AMD_STONEYRIDGE),y) diff --git a/src/soc/amd/stoneyridge/Makefile.mk b/src/soc/amd/stoneyridge/Makefile.mk new file mode 100644 index 0000000000..c1c74ea2ea --- /dev/null +++ b/src/soc/amd/stoneyridge/Makefile.mk @@ -0,0 +1,192 @@ +# SPDX-License-Identifier: BSD-3-Clause + +ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) + +subdirs-y += ../../../cpu/amd/mtrr/ + +bootblock-y += aoac.c +bootblock-y += BiosCallOuts.c +bootblock-y += bootblock.c +bootblock-y += early_fch.c +bootblock-y += gpio.c +bootblock-y += i2c.c +bootblock-y += enable_usbdebug.c + +romstage-y += BiosCallOuts.c +romstage-y += i2c.c +romstage-y += romstage.c +romstage-y += enable_usbdebug.c +romstage-y += fch_agesa.c +romstage-y += gpio.c +romstage-y += smbus_spd.c +romstage-y += memmap.c +romstage-y += psp.c + +verstage-y += gpio.c +verstage-y += i2c.c + +postcar-y += memmap.c +postcar-$(CONFIG_TPM_MEASURED_BOOT) += i2c.c + +ramstage-y += aoac.c +ramstage-y += BiosCallOuts.c +ramstage-y += i2c.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += mca.c +ramstage-y += enable_usbdebug.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-y += fch.c +ramstage-y += fch_agesa.c +ramstage-y += gpio.c +ramstage-y += graphics.c +ramstage-y += northbridge.c +ramstage-y += sata.c +ramstage-y += memmap.c +ramstage-y += usb.c +ramstage-y += psp.c + +all-y += monotonic_timer.c +all-y += pstate_util.c +all-y += reset.c +all-y += tsc_freq.c +all-y += uart.c + +smm-y += pstate_util.c +smm-y += monotonic_timer.c +smm-y += smihandler.c +smm-y += tsc_freq.c +smm-$(CONFIG_DEBUG_SMI) += uart.c +smm-y += gpio.c +smm-y += psp.c + +CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include +CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/acpi + +# ROMSIG Normally At ROMBASE + 0x20000 +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# |PSPDIR ADDR| +# +-----------+ +# +# EC ROM should be 64K aligned. +### 0 + +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') + +ifneq ($(FIRMWARE_LOCATION),) + +ifeq ($(CONFIG_AMD_APU_STONEYRIDGE),y) +FIRMWARE_TYPE=ST +else +ifeq ($(CONFIG_AMD_APU_MERLINFALCON),y) +FIRMWARE_TYPE=CZ +else +ifeq ($(CONFIG_AMD_APU_PRAIRIEFALCON),y) +FIRMWARE_TYPE=ST +else +$(error soc/amd/stoneyridge: Unusable FIRMWARE_TYPE) + +endif # CONFIG_AMD_APU_PRAIRIEFALCON +endif # CONFIG_AMD_APU_MERLINFALCON +endif # CONFIG_AMD_APU_STONEYRIDGE + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) +OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE), --gec) + +SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATION)/$(shell awk '($$1=="PSP_SMUFW1_SUB0_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) +SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATION)/$(shell awk '($$1=="PSP_SMUFW1_SUB1_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) + +SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATION)/$(shell awk '($$1=="PSP_SMUFW2_SUB0_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) +SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATION)/$(shell awk '($$1=="PSP_SMUFW2_SUB1_FILE") {print $$2}' $(CONFIG_AMDFW_CONFIG_FILE)) + +ifeq ("$(wildcard $(SMUFWM_FN_FILE))","") +SMUFWM_FN_FILE= +SMUFIRMWARE2_FN_FILE= +endif + +ifeq ($(CONFIG_USE_PSPSECUREOS),y) +PSP_USE_PSPSECUREOS="--use-pspsecureos" +endif + +OPT_PSP_USE_PSPSECUREOS=$(call strip_quotes, $(PSP_USE_PSPSECUREOS)) + +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) + +$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ + $(DEP_FILES) \ + $(AMDFWTOOL) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(OPT_STONEYRIDGE_XHCI_FWM_FILE) \ + $(OPT_STONEYRIDGE_GEC_FWM_FILE) \ + $(OPT_PSP_USE_PSPSECUREOS) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_DEBUG_AMDFWTOOL) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --flashsize $(CONFIG_ROM_SIZE) \ + --location $(CONFIG_AMD_FWM_POSITION) \ + --output $@ + +ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) + +$(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) + printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ + "$(CONFIG_AMD_FWM_POSITION)" + dd if=$(obj)/amdfw.rom \ + of=$< conv=notrunc bs=1 \ + seek=$(CONFIG_AMD_FWM_POSITION) >/dev/null 2>&1 + +else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) + +STONEYRIDGE_FWM_POSITION=$(call int-add, \ + $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) \ + 1 \ + $(CONFIG_AMD_FWM_POSITION)) +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION) +apu/amdfw-type := raw + +endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) + +ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) + +cbfs-files-y += smu_fw +cbfs-files-y += smu_fw2 +smu_fw-type := raw +smu_fw2-type := raw + +ifeq ($(CONFIG_SOC_AMD_SMU_FANLESS),y) +smu_fw-file := $(SMUFWM_FN_FILE) +smu_fw2-file := $(SMUFIRMWARE2_FN_FILE) +else ifeq ($(CONFIG_SOC_AMD_SMU_FANNED),y) +smu_fw-file := $(SMUFWM_FILE) +smu_fw2-file := $(SMUFIRMWARE2_FILE) +else +$(error "Proper SMU Firmware not selected") +endif + +endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) + +else # ifneq ($(FIRMWARE_LOCATION),) + +warn_no_amdfw: + printf "\n\t** WARNING **\n" + printf "coreboot has been built with no PSP firmware and " + printf "a non-booting image has been generated.\n\n" + +PHONY+=warn_no_amdfw + +show_notices:: warn_no_amdfw + +endif # ifneq ($(FIRMWARE_LOCATION),) + +endif # ($(CONFIG_SOC_AMD_STONEYRIDGE),y) -- cgit v1.2.3