From b0f81518b5c17466bc95ebdef292e82c4b76bc88 Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Mon, 25 Jul 2016 21:31:41 -0500
Subject: chromeos mainboards: remove chromeos.asl

Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package.  Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.

Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
---
 src/soc/intel/apollolake/include/soc/gpio_defs.h | 6 ++++++
 src/soc/intel/baytrail/include/soc/gpio.h        | 2 ++
 src/soc/intel/braswell/include/soc/gpio.h        | 2 ++
 src/soc/intel/broadwell/include/soc/gpio.h       | 3 +++
 src/soc/intel/skylake/include/soc/gpio.h         | 2 ++
 5 files changed, 15 insertions(+)

(limited to 'src/soc')

diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h
index 48e08e783e..aa1ce8cf65 100644
--- a/src/soc/intel/apollolake/include/soc/gpio_defs.h
+++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h
@@ -362,6 +362,12 @@
 #define PAD_W(pad)			(pad - W_OFFSET)
 #define PAD_SW(pad)			(pad - SW_OFFSET)
 
+/* Linux names of the GPIO devices. */
+#define GPIO_COMM_N_NAME		"INT3452:00"
+#define GPIO_COMM_NW_NAME		"INT3452:01"
+#define GPIO_COMM_W_NAME		"INT3452:02"
+#define GPIO_COMM_SW_NAME		"INT3452:03"
+
 /* Default configurations */
 #define PAD_CFG0_DEFAULT_FUNC(x)	(PAD_CFG0_RESET_DEEP | PAD_CFG0_MODE_FUNC(x))
 #define PAD_CFG0_DEFAULT_NATIVE		PAD_CFG0_DEFAULT_FUNC(1)
diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h
index 79c19b4f4d..3757eb012c 100644
--- a/src/soc/intel/baytrail/include/soc/gpio.h
+++ b/src/soc/intel/baytrail/include/soc/gpio.h
@@ -22,6 +22,8 @@
 
 /* #define GPIO_DEBUG */
 
+#define CROS_GPIO_DEVICE_NAME	"BayTrail"
+
 /* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */
 #define GPSCORE_PAD_BASE	(IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
 #define GPNCORE_PAD_BASE	(IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE)
diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index c7bfb65d65..3c56f6ae32 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -22,6 +22,8 @@
 #include <soc/gpio_defs.h>
 #include <soc/iomap.h>
 
+#define CROS_GPIO_DEVICE_NAME "Braswell"
+
 #define COMMUNITY_SIZE	0x20000
 
 #define COMMUNITY_GPSOUTHWEST_BASE	\
diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h
index 7345df5257..ff51283709 100644
--- a/src/soc/intel/broadwell/include/soc/gpio.h
+++ b/src/soc/intel/broadwell/include/soc/gpio.h
@@ -18,6 +18,9 @@
 
 #include <stdint.h>
 
+#define CROS_GPIO_DEVICE_NAME		"PCH-LP"
+#define CROS_GPIO_ACPI_DEVICE_NAME	"INT3437:00"
+
 /* PCH-LP GPIOBASE Registers */
 #define GPIO_OWNER(set)		(0x00 + ((set) * 4))
 #define GPIO_PIRQ_APIC_EN	0x10
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index 6733889d1a..d86af0f54a 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -19,6 +19,8 @@
 
 #include <soc/gpio_defs.h>
 
+#define CROS_GPIO_DEVICE_NAME	"INT344B:00"
+
 #ifndef __ACPI__
 #include <stdint.h>
 #include <stddef.h>
-- 
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