From ae81497cb6c7a7d1c4dde837cb84a196752c57bf Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 10 May 2023 18:06:27 +0200 Subject: device/pci: Limit default domain memory window When the default pci_domain_read_resources() is used, keep 32-bit memory resources below the limit given by CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT. This serves as a workaround for missing/wrong reservations of chipset resources. This will help to get more stable results from our own allocator, but is far from a complete solution. Indvi- dual platform ASL code also needs to be considered, so the OS won't assign conflicting resources. Most platforms have reserved space between 0xfe000000 and the 4G barrier. So use that as a global default. In case of `soc/intel/common/`, use 0xe0000000 because this is what is advertised in ACPI and there are traces of resources below 0xfe000000 that are unknown to core- boot's C code (PCH_PRESERVED_BASE?). Tested on QEMU/Q35 and Siemens/Chili w/ and w/o top- down allocation. Fixes EHCI w/ top-down in QEMU. Change-Id: Iae0d888eebd0ec11a9d6f12975ae24dc32a80d8c Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/75102 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/systemagent/Kconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index d8c217f25a..4d14fc127e 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -6,6 +6,9 @@ config SOC_INTEL_COMMON_BLOCK_SA if SOC_INTEL_COMMON_BLOCK_SA +config DOMAIN_RESOURCE_32BIT_LIMIT + default 0xe0000000 + config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -- cgit v1.2.3