From ae695757f43a5a730e16132ab830d76c10ba8daf Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 12 Nov 2019 12:47:43 +0530 Subject: soc/intel/tigerlake: Include few more Tigerlake device IDs This patch performs below operations 1. Add few more MCH, ESPI and IGD IDs 2. Remove TGL-H IDs 3. Rename existing as per applicable names 4. Remove TODO from report_platform.c file 5. Include TGL IDs into report_platform.c file Change-Id: I7bb3334d0fe8ba72e394d1a63b3a73840b4eaf2f Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36768 Tested-by: build bot (Jenkins) Reviewed-by: Maulik V Vaghela --- src/soc/intel/common/block/graphics/graphics.c | 8 +-- src/soc/intel/common/block/lpc/lpc.c | 33 ++++++++++- .../intel/common/block/systemagent/systemagent.c | 1 + .../intel/tigerlake/bootblock/report_platform.c | 66 +++++++++++++++++++++- 4 files changed, 100 insertions(+), 8 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 4efa60f5d2..df838c0c88 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -207,10 +207,10 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CML_GT1_H_2, PCI_DEVICE_ID_INTEL_CML_GT2_H_1, PCI_DEVICE_ID_INTEL_CML_GT2_H_2, - PCI_DEVICE_ID_INTEL_TGL_GT1, - PCI_DEVICE_ID_INTEL_TGL_GT2_UY, - PCI_DEVICE_ID_INTEL_TGL_GT2, - PCI_DEVICE_ID_INTEL_TGL_GT2_Y, + PCI_DEVICE_ID_INTEL_TGL_GT0, + PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, + PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, + PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, 0, }; diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index c2b51bec9b..249e6d6256 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -190,7 +190,38 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC, PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC, - PCI_DEVICE_ID_INTEL_TGL_ESPI, + PCI_DEVICE_ID_INTEL_TGP_ESPI_0, + PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI, + PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI, + PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI, + PCI_DEVICE_ID_INTEL_TGP_ESPI_1, + PCI_DEVICE_ID_INTEL_TGP_ESPI_2, + PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI, + PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI, + PCI_DEVICE_ID_INTEL_TGP_ESPI_3, + PCI_DEVICE_ID_INTEL_TGP_ESPI_4, + PCI_DEVICE_ID_INTEL_TGP_ESPI_5, + PCI_DEVICE_ID_INTEL_TGP_ESPI_6, + PCI_DEVICE_ID_INTEL_TGP_ESPI_7, + PCI_DEVICE_ID_INTEL_TGP_ESPI_8, + PCI_DEVICE_ID_INTEL_TGP_ESPI_9, + PCI_DEVICE_ID_INTEL_TGP_ESPI_10, + PCI_DEVICE_ID_INTEL_TGP_ESPI_11, + PCI_DEVICE_ID_INTEL_TGP_ESPI_12, + PCI_DEVICE_ID_INTEL_TGP_ESPI_13, + PCI_DEVICE_ID_INTEL_TGP_ESPI_14, + PCI_DEVICE_ID_INTEL_TGP_ESPI_15, + PCI_DEVICE_ID_INTEL_TGP_ESPI_16, + PCI_DEVICE_ID_INTEL_TGP_ESPI_17, + PCI_DEVICE_ID_INTEL_TGP_ESPI_18, + PCI_DEVICE_ID_INTEL_TGP_ESPI_19, + PCI_DEVICE_ID_INTEL_TGP_ESPI_20, + PCI_DEVICE_ID_INTEL_TGP_ESPI_21, + PCI_DEVICE_ID_INTEL_TGP_ESPI_22, + PCI_DEVICE_ID_INTEL_TGP_ESPI_23, + PCI_DEVICE_ID_INTEL_TGP_ESPI_24, + PCI_DEVICE_ID_INTEL_TGP_ESPI_25, + PCI_DEVICE_ID_INTEL_TGP_ESPI_26, 0 }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 7ad565d8e8..5f7d5af82c 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -363,6 +363,7 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_CML_H, PCI_DEVICE_ID_INTEL_CML_H_8_2, PCI_DEVICE_ID_INTEL_TGL_ID_U, + PCI_DEVICE_ID_INTEL_TGL_ID_U_1, PCI_DEVICE_ID_INTEL_TGL_ID_Y, 0 }; diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 6a58ea7c97..41061ee03b 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -33,9 +33,69 @@ #define BIOS_SIGN_ID 0x8B -/* - * TODO: Add TGL specific CPU/SA/PCH IDs here - */ +static struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, +}; + +static struct { + u16 espiid; + const char *name; +} pch_table[] = { + { PCI_DEVICE_ID_INTEL_TGP_ESPI_0, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI, "Tigerlake-U Super SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI, "Tigerlake-U Premium SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI, "Tigerlake-U Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_1, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_2, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI, "Tigerlake-Y Super SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI, "Tigerlake-Y Premium SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_3, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_4, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_5, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_6, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_7, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_8, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_9, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_10, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_11, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_12, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_13, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_14, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_15, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_16, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_17, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_18, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_19, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_20, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_21, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_22, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_23, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, + { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DEVICE_ID_INTEL_TGL_GT0, "Tigerlake U GT0" }, + { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, + { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, + { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, +}; static inline uint8_t get_dev_revision(pci_devfn_t dev) { -- cgit v1.2.3