From adc4753a8d8c5dc7462547ab148c2d63eabbe4fa Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 28 Dec 2018 15:48:58 +0100 Subject: usbdebug: Make the EHCI debug console work in the bootblock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently this needlessly initializes the hardware in the both the romstage and the bootblock, but it works. Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the use better, related support files can be built to pre-ram stages regardless of usbdebug being enabled or not. Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK). Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f Signed-off-by: Arthur Heymans Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30480 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/amd/stoneyridge/Makefile.inc | 3 ++- src/soc/intel/broadwell/Makefile.inc | 3 ++- src/soc/intel/fsp_baytrail/romstage/romstage.c | 2 +- src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 2 +- 4 files changed, 6 insertions(+), 4 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index a53984e4a3..0f6290bc49 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -42,6 +42,7 @@ bootblock-y += BiosCallOuts.c bootblock-y += bootblock/bootblock.c bootblock-y += gpio.c bootblock-y += i2c.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c bootblock-y += monotonic_timer.c bootblock-y += pmutil.c bootblock-y += reset.c @@ -55,7 +56,7 @@ bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c romstage-y += BiosCallOuts.c romstage-y += i2c.c romstage-y += romstage.c -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c +romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += gpio.c romstage-y += monotonic_timer.c romstage-y += pmutil.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index caf963c8e0..acb71fe7d7 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -61,7 +61,8 @@ ramstage-y += systemagent.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-y += tsc_freq.c -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c +bootblock-$(CONFIG_USBDEBUG) += usb_debug.c +romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-y += ehci.c ramstage-y += xhci.c diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 15ab9ec949..19a0d44ecb 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -227,7 +227,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) __func__, (u32) status, (u32) hob_list_ptr); /* FSP reconfigures USB, so reinit it to have debug */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)) + if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 924aab2a25..003ae2270c 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -103,7 +103,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) __func__, (u32) status, (u32) hob_list_ptr); /* FSP reconfigures USB, so reinit it to have debug */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)) + if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); -- cgit v1.2.3