From ad5e0a8e65b391706ed04227214f1d4eb4f63763 Mon Sep 17 00:00:00 2001
From: Frans Hendriks <fhendriks@eltan.com>
Date: Mon, 18 Mar 2019 13:31:56 +0100
Subject: soc/intel/braswell: Reserve IOAPIC and ROM resources

The mmio resouces IOAPIC and ROM area not reserved.
Reserve IOAPIC and ROM resources.

BUG=N/A
TEST=Intel CherryHill CRB booting Embedded Linux

Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
 src/soc/intel/braswell/southcluster.c | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/soc')

diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index f389084795..b8263db6b7 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -20,6 +20,7 @@
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <arch/acpi.h>
+#include <arch/ioapic.h>
 #include <bootstate.h>
 #include "chip.h"
 #include <console/console.h>
@@ -74,6 +75,10 @@ static void sc_add_mmio_resources(struct device *dev)
 	add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE);
 	add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE);
 	add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE);
+	add_mmio_resource(dev, 0xfff,
+		0xffffffff - (CONFIG_COREBOOT_ROMSIZE_KB*KiB) + 1,
+		(CONFIG_COREBOOT_ROMSIZE_KB*KiB));	/* BIOS ROM */
+	add_mmio_resource(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */
 }
 
 /* Default IO range claimed by the LPC device. The upper bound is exclusive. */
-- 
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