From ad1e49afacae6e38cc7d735f67b6f2afb6d9fb71 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 29 Nov 2018 16:24:24 -0800 Subject: soc/intel/common: Limit BIOS region cache to 16MB Cache BIOS region can boost boot performance, however it can't be over 16MB, according to processor EDS vol1(Apollolake/Skylake/WhiskeyLake), FLASH+APIC LT will be less than 20MB under 4G. Set the maxiam to 16GB to save numbers of mtrr entries. BUG=b:119267832 TEST=Build and boot up fine on whiskeylake rvp platform. Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/c/29944 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/fast_spi/fast_spi.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 5ff0872a4f..ae4abc8ff1 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -240,6 +240,12 @@ void fast_spi_cache_bios_region(void) if (!bios_size) return; + /* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will + * cause memory type conflict when setting memory type to write + * protection, so limit the cached bios region to be no more than 16MB. + * */ + bios_size = MIN(bios_size, 16 * MiB); + /* Round to power of two */ alignment = 1UL << (log2_ceil(bios_size)); bios_size = ALIGN_UP(bios_size, alignment); -- cgit v1.2.3