From ab83b43b34d729ad260d8f68b725ed025eaafb5e Mon Sep 17 00:00:00 2001 From: Matt Papageorge Date: Fri, 26 Jun 2020 08:47:00 -0500 Subject: soc/amd/picasso/sb: Gate FCH AL2AHB clocks Gate the A-Link to AHB Bridge clocks to save power. These are internal clocks and are unneeded for Raven/Picasso. This was previously performed within the AGESA FSP but this change relocates it into coreboot. BUG=b:154144239 TEST=Check AL2AHB clock gate bits at the end of POST before and after change with HDT. Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9 Signed-off-by: Matt Papageorge Reviewed-on: https://review.coreboot.org/c/coreboot/+/42829 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh --- src/soc/amd/picasso/include/soc/iomap.h | 5 +++++ src/soc/amd/picasso/southbridge.c | 18 ++++++++++++++++++ 2 files changed, 23 insertions(+) (limited to 'src/soc') diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index cb845c44d3..6b9ad2a005 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -12,7 +12,12 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 +/* FCH AL2AHB Registers */ #define ALINK_AHB_ADDRESS 0xfedc0000 +#define AL2AHB_CONTROL_CLK_OFFSET 0x10 +#define AL2AHB_CLK_GATE_EN (1 << 1) +#define AL2AHB_CONTROL_HCLK_OFFSET 0x30 +#define AL2AHB_HCLK_GATE_EN (1 << 1) /* Reserved 0xfecd1000-0xfedc3fff */ diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index cb22195546..4cd24dd900 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -328,11 +328,29 @@ static void set_nvs_sws(void *unused) BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); +/* + * A-Link to AHB bridge, part of the AMBA fabric. These are internal clocks + * and unneeded for Raven/Picasso so gate them to save power. + */ +static void al2ahb_clock_gate(void) +{ + uint8_t al2ahb_val; + uintptr_t al2ahb_base = ALINK_AHB_ADDRESS; + + al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET)); + al2ahb_val |= AL2AHB_CLK_GATE_EN; + write8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET), al2ahb_val); + al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET)); + al2ahb_val |= AL2AHB_HCLK_GATE_EN; + write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val); +} + void southbridge_init(void *chip_info) { i2c_soc_init(); sb_init_acpi_ports(); acpi_clear_pm1_status(); + al2ahb_clock_gate(); } static void set_sb_final_nvs(void) -- cgit v1.2.3