From a94fea1ee444b8f1359729064cd72c963d36ad3f Mon Sep 17 00:00:00 2001 From: Nina Wu Date: Tue, 16 Mar 2021 14:29:12 +0800 Subject: vendorcode/mt8192: devapc: fix register offset for PCIe domain Correct the wrong offset for setting PCIe domain. Change-Id: I9de2bdf5a0a4fb5b34985b11976fd50b397e97ba Signed-off-by: Nina Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/51512 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8192/devapc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc') diff --git a/src/soc/mediatek/mt8192/devapc.c b/src/soc/mediatek/mt8192/devapc.c index 9e3692e634..542c05f633 100644 --- a/src/soc/mediatek/mt8192/devapc.c +++ b/src/soc/mediatek/mt8192/devapc.c @@ -13,7 +13,7 @@ static void infra_master_init(uintptr_t base) SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, 1, CPU_EB_SEC, 1); /* Domain */ - SET32_BITFIELDS(getreg(base, MAS_SEC_0), PCIE_DOM, MAS_DOMAIN_1); + SET32_BITFIELDS(getreg(base, MAS_DOM_0), PCIE_DOM, MAS_DOMAIN_1); SET32_BITFIELDS(getreg(base, MAS_DOM_1), SCP_SSPM_DOM, MAS_DOMAIN_2, CPU_EB_DOM, MAS_DOMAIN_2); -- cgit v1.2.3