From a486af46b2a5d49b05bfc89a876b5c800eadbe69 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Thu, 1 Oct 2015 16:12:23 +0530 Subject: soc/qualcomm/ipq40xx: Add coreboot Table entry for serial console BUG=chrome-os-partner:49249 TEST=Compiles... BRANCH=none Change-Id: I76a24bc9b3cec53d5c10ecd86e5c8e45285e9632 Signed-off-by: Patrick Georgi Original-Commit-Id: 4ab1717ff020d564abffcee208b6587e1ae2f950 Original-Change-Id: I2d155e80424d1c1837eb35703bd42ff3244e112a Original-Signed-off-by: Varadarajan Narayanan Original-Reviewed-on: https://chromium-review.googlesource.com/333306 Original-Commit-Ready: David Hendricks Original-Reviewed-by: David Hendricks Reviewed-on: https://review.coreboot.org/14662 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/qualcomm/ipq40xx/uart.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/soc') diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 99b2b055b7..cb96a2655d 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -402,5 +402,14 @@ uint8_t uart_rx_byte(int idx) /* TODO: Implement function */ void uart_fill_lb(void *data) { + struct lb_serial serial; + + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = (uint32_t)UART1_DM_BASE; + serial.baud = default_baudrate(); + serial.regwidth = 1; + + lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif -- cgit v1.2.3