From a47ab1be121004a88a8c680f218ad0f04a374901 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Wed, 16 Jul 2014 19:02:20 +1000 Subject: soc,Makefile.inc: Trivial - drop trailing blank lines at EOF Change-Id: I6db4eada5be5f9a4340d9edb942924e2fd18b5ca Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/6284 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering --- src/soc/intel/fsp_baytrail/Makefile.inc | 1 - src/soc/intel/fsp_baytrail/fsp/Makefile.inc | 1 - 2 files changed, 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index e0f1e1dfc0..598deb4b33 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -87,4 +87,3 @@ endif endif endif - diff --git a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc index ebdc80a721..05620aedcc 100644 --- a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc @@ -19,4 +19,3 @@ ramstage-y += chipset_fsp_util.c romstage-y += chipset_fsp_util.c - -- cgit v1.2.3