From 9c51ca52a447217c394717fde2bc97f64afd6781 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 17 Sep 2024 15:06:50 +0200 Subject: soc/intel/ehl/fsp_params: Do not re-enable 'PchPwrOptEnable' for real-time tuning If real-time tuning was enabled, 'PchPwrOptEnable' was set two times with different values. This patch fixes the issue. BUG=none TEST=Enabled FSP UPD debug output and checked 'PchPwrOptEnable' offset Change-Id: I2f31015c1da51a4ae1b8d5226f5d7b60a6023f3d Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/84399 Reviewed-by: Werner Zeh Tested-by: build bot (Jenkins) --- src/soc/intel/elkhartlake/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc') diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 5e1bba78ea..90d1823f50 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -333,6 +333,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->D3ColdEnable = 0; params->PmcOsIdleEnable = 0; } else { + params->PchPwrOptEnable = 1; /* Enable PCH DMI Power Optimizer */ params->PchPostMasterClockGating = 1; params->PchPostMasterPowerGating = 1; } @@ -471,7 +472,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Custom1TurboActivationRatio = 0; params->Custom2TurboActivationRatio = 0; params->Custom3TurboActivationRatio = 0; - params->PchPwrOptEnable = 0x1; //Enable PCH DMI Power Optimizer params->TStates = 0x0; //Disable T state params->PkgCStateLimit = 0x7; //Set C state limit to C9 params->FastPkgCRampDisable[0] = 0x1; -- cgit v1.2.3