From 9c1c00968c943659bab2a817892e5a9be9dfb7c0 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Wed, 29 Jul 2020 20:48:08 +0200 Subject: soc/intel/skylake: Enable thermal subsystem depending on devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently SA thermal subsystem gets enabled by the option Device4Enable, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the SA thermal subsystem controller. All corresponding mainboards were checked if the devicetree configuration matches the Device4Enable setting, and missing entries were added. Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/chip.c | 4 +++- src/soc/intel/skylake/chip.h | 1 - 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 562d791a6d..6423cf4120 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -278,7 +278,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; - params->Device4Enable = config->Device4Enable; + + dev = pcidev_path_on_root(SA_DEVFN_TS); + params->Device4Enable = dev && dev->enabled; params->EnableTcoTimer = !config->PmTimerDisabled; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index fc86cfd58f..e332a6bb8e 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -336,7 +336,6 @@ struct soc_intel_skylake_config { u32 LogoPtr; u32 LogoSize; u32 GraphicsConfigPtr; - u8 Device4Enable; u8 RtcLock; /* GPIO IRQ Route The valid values is 14 or 15*/ u8 GpioIrqSelect; -- cgit v1.2.3