From 9c0e14e7c43e85e99c0bbfdff72019d908de1711 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 23 Jan 2019 16:46:35 +0200 Subject: device/pci_ops: Define pci_find_capability() just once MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Wrap the simple romstage implementation to be called from ramstage. Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31755 Reviewed-by: Paul Menzel Reviewed-by: Martin Roth Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/cavium/common/ecam.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'src/soc') diff --git a/src/soc/cavium/common/ecam.c b/src/soc/cavium/common/ecam.c index ae2a91fe0d..89c69dbc2e 100644 --- a/src/soc/cavium/common/ecam.c +++ b/src/soc/cavium/common/ecam.c @@ -17,6 +17,8 @@ * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ +#define __SIMPLE_DEVICE__ + #include #include #include @@ -27,15 +29,11 @@ * Get PCI BAR address from cavium specific extended capability. * Use regular BAR if not found in extended capability space. * - * @return The pyhsical address of the BAR, zero on error + * @return The physical address of the BAR, zero on error */ -#ifdef __SIMPLE_DEVICE__ uint64_t ecam0_get_bar_val(pci_devfn_t dev, u8 bar) -#else -uint64_t ecam0_get_bar_val(struct device *dev, u8 bar) -#endif { - size_t cap_offset = pci_find_capability(dev, 0x14); + size_t cap_offset = pci_s_find_capability(dev, 0x14); uint64_t h, l, ret = 0; if (cap_offset) { /* Found EA */ -- cgit v1.2.3