From 9abc3fe9705764904b6439672cefc859ca3ab278 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Thu, 28 Jun 2018 16:31:45 -0600 Subject: stoneyridge: Enable legacy IO Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to function correctly. BUG=b:110817463 TEST=ran firmware_CorruptFwSigB on grunt Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Signed-off-by: Raul E Rangel Reviewed-on: https://review.coreboot.org/27268 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/stoneyridge/include/soc/southbridge.h | 1 + src/soc/amd/stoneyridge/southbridge.c | 8 ++++++++ 2 files changed, 9 insertions(+) (limited to 'src/soc') diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 9f8a7d2f4b..3127f5cd47 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -34,6 +34,7 @@ /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ #define PM_DECODE_EN 0x00 #define CF9_IO_EN BIT(1) +#define LEGACY_IO_EN BIT(0) #define PM_ISA_CONTROL 0x04 #define MMIO_EN BIT(1) #define PM_PCI_CTRL 0x08 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 591a8f7c9f..18e6c6c59d 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -375,6 +375,13 @@ static void sb_enable_cf9_io(void) pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); } +static void sb_enable_legacy_io(void) +{ + uint32_t reg = pm_read32(PM_DECODE_EN); + + pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); +} + void sb_clk_output_48Mhz(void) { u32 ctrl; @@ -550,6 +557,7 @@ void bootblock_fch_early_init(void) sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ sb_acpi_mmio_decode(); sb_enable_cf9_io(); + sb_enable_legacy_io(); enable_aoac_devices(); } -- cgit v1.2.3