From 99aa6ce053f5122a98713b8353de6b8a72182cad Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 24 Jun 2017 21:34:58 -0600 Subject: src/soc: add IS_ENABLED() around Kconfig symbol references MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I2e7b756296e861e08cea846297f687a880daaf45 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/20355 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/broadcom/cygnus/ddr_init.c | 8 +-- src/soc/dmp/vortex86ex/ide_sd_sata.c | 8 +-- src/soc/dmp/vortex86ex/raminit.c | 2 +- src/soc/dmp/vortex86ex/southbridge.c | 78 +++++++++++----------- src/soc/mediatek/mt8173/i2c.c | 2 +- src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h | 2 +- src/soc/mediatek/mt8173/mt6391.c | 2 +- src/soc/nvidia/tegra210/include/soc/mtc.h | 2 +- src/soc/nvidia/tegra210/romstage.c | 2 +- 9 files changed, 53 insertions(+), 53 deletions(-) (limited to 'src/soc') diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index 5c4c985366..1a5fd86bb0 100644 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -475,7 +475,7 @@ int is_ddr_32bit(void) { int ddr32 = 0; -#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) +#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) ddr32=1; #endif /* (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) */ @@ -966,7 +966,7 @@ static int try_restore_shmoo(void) reg = (uint32_t *)(*flptr++); val = (uint32_t *)(*flptr++); if ( (((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114))) -#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS)) +#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS) || (((uint32_t)reg >= DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + 0x114))) #endif #ifdef CONFIG_IPROC_DDR_ECC @@ -1068,7 +1068,7 @@ void iproc_save_shmoo_values(void) *ptr++ = val; chksum += val; } -#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS)) +#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS) if (is_ddr_32bit()) { for (i=0; i 0) & (DDR_AUTO_SELF_REFRESH_IDLE_COUNT <= 0xff) /* Enable auto self-refresh */ reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57, diff --git a/src/soc/dmp/vortex86ex/ide_sd_sata.c b/src/soc/dmp/vortex86ex/ide_sd_sata.c index 936505e436..c60018ab49 100644 --- a/src/soc/dmp/vortex86ex/ide_sd_sata.c +++ b/src/soc/dmp/vortex86ex/ide_sd_sata.c @@ -80,20 +80,20 @@ static void init_ide_ata_timing(struct device *dev) u16 ata_timing_pri, ata_timing_sec; u32 ata_timing_reg32; /* Primary channel is SD. */ -#if CONFIG_IDE1_ENABLE +#if IS_ENABLED(CONFIG_IDE1_ENABLE) ata_timing_pri = 0x8000; #else ata_timing_pri = 0x0000; // Disable this channel. #endif /* Secondary channel is SATA. */ -#if CONFIG_IDE2_ENABLE +#if IS_ENABLED(CONFIG_IDE2_ENABLE) ata_timing_sec = 0xa30f; // This setting value works well. #else ata_timing_sec = 0x0000; // Disable this channel. #endif ata_timing_reg32 = (ata_timing_sec << 16) | ata_timing_pri; pci_write_config32(dev, 0x40, ata_timing_reg32); -#if CONFIG_IDE_NATIVE_MODE +#if IS_ENABLED(CONFIG_IDE_NATIVE_MODE) /* Set both IDE channels to native mode. */ u8 prog_if; prog_if = pci_read_config8(dev, 0x09); @@ -110,7 +110,7 @@ static void init_ide_ata_timing(struct device *dev) static void setup_std_ide_compatible(struct device *dev) { -#if CONFIG_IDE_STANDARD_COMPATIBLE +#if IS_ENABLED(CONFIG_IDE_STANDARD_COMPATIBLE) // Misc Control Register (MCR) Offset 90h // bit 0 = Vendor ID Access, bit 1 = Device ID Access. u8 mcr; diff --git a/src/soc/dmp/vortex86ex/raminit.c b/src/soc/dmp/vortex86ex/raminit.c index 1ccdb27e7e..0d4b5b56b3 100644 --- a/src/soc/dmp/vortex86ex/raminit.c +++ b/src/soc/dmp/vortex86ex/raminit.c @@ -253,7 +253,7 @@ static u8 detect_ddr3_dram_size(void) static void print_ddr3_memory_setup(void) { -#if CONFIG_DEBUG_RAM_SETUP +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) printk(BIOS_DEBUG, "DDR3 Timing Reg 0-3:\n"); printk(BIOS_DEBUG, "NB 6e : "); print_debug_hex16(pci_read_config16(NB, 0x6e)); diff --git a/src/soc/dmp/vortex86ex/southbridge.c b/src/soc/dmp/vortex86ex/southbridge.c index 05702d1eb6..451aea67c0 100644 --- a/src/soc/dmp/vortex86ex/southbridge.c +++ b/src/soc/dmp/vortex86ex/southbridge.c @@ -207,7 +207,7 @@ static void pci_routing_fixup(struct device *dev) ext_int_routing |= irq_to_int_routing[CAN_IRQ] << CAN_IRQ_SHIFT; ext_int_routing |= irq_to_int_routing[HDA_IRQ] << HDA_IRQ_SHIFT; ext_int_routing |= irq_to_int_routing[USBD_IRQ] << USBD_IRQ_SHIFT; -#if CONFIG_IDE_NATIVE_MODE +#if IS_ENABLED(CONFIG_IDE_NATIVE_MODE) /* IDE in native mode, only uses one IRQ. */ ext_int_routing |= irq_to_int_routing[0] << SIDE_IRQ_SHIFT; ext_int_routing |= irq_to_int_routing[PIDE_IRQ] << PIDE_IRQ_SHIFT; @@ -250,21 +250,21 @@ static void vortex_sb_init(struct device *dev) { u32 lpt_reg = 0; -#if CONFIG_LPT_ENABLE +#if IS_ENABLED(CONFIG_LPT_ENABLE) int ppmod = 0; -#if CONFIG_LPT_MODE_BPP +#if IS_ENABLED(CONFIG_LPT_MODE_BPP) ppmod = 0; -#elif CONFIG_LPT_MODE_EPP_19_AND_SPP +#elif IS_ENABLED(CONFIG_LPT_MODE_EPP_19_AND_SPP) ppmod = 1; -#elif CONFIG_LPT_MODE_ECP +#elif IS_ENABLED(CONFIG_LPT_MODE_ECP) ppmod = 2; -#elif CONFIG_LPT_MODE_ECP_AND_EPP_19 +#elif IS_ENABLED(CONFIG_LPT_MODE_ECP_AND_EPP_19) ppmod = 3; -#elif CONFIG_LPT_MODE_SPP +#elif IS_ENABLED(CONFIG_LPT_MODE_SPP) ppmod = 4; -#elif CONFIG_LPT_MODE_EPP_17_AND_SPP +#elif IS_ENABLED(CONFIG_LPT_MODE_EPP_17_AND_SPP) ppmod = 5; -#elif CONFIG_LPT_MODE_ECP_AND_EPP_17 +#elif IS_ENABLED(CONFIG_LPT_MODE_ECP_AND_EPP_17) ppmod = 7; #else #error CONFIG_LPT_MODE error. @@ -303,67 +303,67 @@ static void ex_sb_gpio_init(struct device *dev) * Bit 31-16 : DBA, GPIO direction base address. * Bit 15-0 : DPBA, GPIO data port base address. * */ -#if CONFIG_GPIO_P0_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P0_ENABLE) SETUP_GPIO_ADDR(0) #endif -#if CONFIG_GPIO_P1_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P1_ENABLE) SETUP_GPIO_ADDR(1) #endif -#if CONFIG_GPIO_P2_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P2_ENABLE) SETUP_GPIO_ADDR(2) #endif -#if CONFIG_GPIO_P3_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P3_ENABLE) SETUP_GPIO_ADDR(3) #endif -#if CONFIG_GPIO_P4_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P4_ENABLE) SETUP_GPIO_ADDR(4) #endif -#if CONFIG_GPIO_P5_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P5_ENABLE) SETUP_GPIO_ADDR(5) #endif -#if CONFIG_GPIO_P6_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P6_ENABLE) SETUP_GPIO_ADDR(6) #endif -#if CONFIG_GPIO_P7_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P7_ENABLE) SETUP_GPIO_ADDR(7) #endif -#if CONFIG_GPIO_P8_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P8_ENABLE) SETUP_GPIO_ADDR(8) #endif -#if CONFIG_GPIO_P9_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P9_ENABLE) SETUP_GPIO_ADDR(9) #endif /* Enable GPIO port 0~9. */ outl(gpio_enable_mask, base); /* Set GPIO port 0-9 initial dir and data. */ -#if CONFIG_GPIO_P0_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P0_ENABLE) INIT_GPIO(0) #endif -#if CONFIG_GPIO_P1_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P1_ENABLE) INIT_GPIO(1) #endif -#if CONFIG_GPIO_P2_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P2_ENABLE) INIT_GPIO(2) #endif -#if CONFIG_GPIO_P3_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P3_ENABLE) INIT_GPIO(3) #endif -#if CONFIG_GPIO_P4_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P4_ENABLE) INIT_GPIO(4) #endif -#if CONFIG_GPIO_P5_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P5_ENABLE) INIT_GPIO(5) #endif -#if CONFIG_GPIO_P6_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P6_ENABLE) INIT_GPIO(6) #endif -#if CONFIG_GPIO_P7_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P7_ENABLE) INIT_GPIO(7) #endif -#if CONFIG_GPIO_P8_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P8_ENABLE) INIT_GPIO(8) #endif -#if CONFIG_GPIO_P9_ENABLE +#if IS_ENABLED(CONFIG_GPIO_P9_ENABLE) INIT_GPIO(9) #endif /* Disable GPIO Port Config IO Base Address. */ @@ -391,34 +391,34 @@ static void ex_sb_uart_init(struct device *dev) /* S/B register 61h - 60h : UART Config IO Base Address */ pci_write_config16(dev, SB_REG_UART_CFG_IO_BASE, base | 1); /* setup UART */ -#if CONFIG_UART1_ENABLE +#if IS_ENABLED(CONFIG_UART1_ENABLE) SETUP_UART(1) #endif -#if CONFIG_UART2_ENABLE +#if IS_ENABLED(CONFIG_UART2_ENABLE) SETUP_UART(2) #endif -#if CONFIG_UART3_ENABLE +#if IS_ENABLED(CONFIG_UART3_ENABLE) SETUP_UART(3) #endif -#if CONFIG_UART4_ENABLE +#if IS_ENABLED(CONFIG_UART4_ENABLE) SETUP_UART(4) #endif -#if CONFIG_UART5_ENABLE +#if IS_ENABLED(CONFIG_UART5_ENABLE) SETUP_UART(5) #endif -#if CONFIG_UART6_ENABLE +#if IS_ENABLED(CONFIG_UART6_ENABLE) SETUP_UART(6) #endif -#if CONFIG_UART7_ENABLE +#if IS_ENABLED(CONFIG_UART7_ENABLE) SETUP_UART(7) #endif -#if CONFIG_UART8_ENABLE +#if IS_ENABLED(CONFIG_UART8_ENABLE) SETUP_UART(8) #endif -#if CONFIG_UART9_ENABLE +#if IS_ENABLED(CONFIG_UART9_ENABLE) SETUP_UART(9) #endif -#if CONFIG_UART10_ENABLE +#if IS_ENABLED(CONFIG_UART10_ENABLE) SETUP_UART(10) #endif /* Keep UART Config I/O base address */ diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 6c04ec3dce..f07ffc92ab 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -70,7 +70,7 @@ static struct mtk_i2c i2c[7] = { #define I2CTAG "[I2C][PL] " -#if CONFIG_DEBUG_I2C +#if IS_ENABLED(CONFIG_DEBUG_I2C) #define I2CLOG(fmt, arg...) printk(BIOS_INFO, I2CTAG fmt, ##arg) #else #define I2CLOG(fmt, arg...) diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h index 1411d39f48..8d449f7950 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h @@ -178,7 +178,7 @@ void dramk_check_dq_win(struct dqs_perbit_dly *p, u8 dly_step, u8 last_step, u32 void tx_delay_for_wrleveling(u32 channel, struct dqs_perbit_dly *dqdqs_perbit_dly, u8 *ave_dqdly_byte, u8 *max_dqsdly_byte); -#if CONFIG_DEBUG_DRAM +#if IS_ENABLED(CONFIG_DEBUG_DRAM) #define dramc_dbg_msg(_x_...) printk(BIOS_DEBUG, _x_) #else #define dramc_dbg_msg(_x_...) diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index ec7fabc554..9ba3503d6b 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -21,7 +21,7 @@ #include #include -#if CONFIG_DEBUG_PMIC +#if IS_ENABLED(CONFIG_DEBUG_PMIC) #define DEBUG_PMIC(level, x...) printk(level, x) #else #define DEBUG_PMIC(level, x...) diff --git a/src/soc/nvidia/tegra210/include/soc/mtc.h b/src/soc/nvidia/tegra210/include/soc/mtc.h index fa07f33247..ca369ad3cf 100644 --- a/src/soc/nvidia/tegra210/include/soc/mtc.h +++ b/src/soc/nvidia/tegra210/include/soc/mtc.h @@ -18,7 +18,7 @@ #include -#if CONFIG_HAVE_MTC +#if IS_ENABLED(CONFIG_HAVE_MTC) int tegra210_run_mtc(void); void soc_add_mtc(struct lb_header *header); diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index 9491570a0b..7b6444d7f8 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -45,7 +45,7 @@ void romstage(void) printk(BIOS_INFO, "T210: romstage here\n"); -#if CONFIG_BOOTROM_SDRAM_INIT +#if IS_ENABLED(CONFIG_BOOTROM_SDRAM_INIT) printk(BIOS_INFO, "T210 romstage: SDRAM init done by BootROM, RAMCODE = %d\n", sdram_get_ram_code()); #else -- cgit v1.2.3