From 94ee328b97a7bf03fa8c80474cce434a2ff43bbd Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Thu, 4 May 2017 13:06:43 -0700 Subject: soc/intel/common/block: Add Intel common SCS code support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Create Intel Common SCS code. This code currently only contains the code for SD card SSDT generation. More code will get added up in the subsequent phases. Change-Id: I82f034ced64e1eaef41a7806133361d73b5009d3 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/19631 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé --- .../intel/common/block/include/intelblocks/sd.h | 27 ++++++++ src/soc/intel/common/block/scs/Kconfig | 4 ++ src/soc/intel/common/block/scs/Makefile.inc | 1 + src/soc/intel/common/block/scs/sd.c | 77 ++++++++++++++++++++++ 4 files changed, 109 insertions(+) create mode 100644 src/soc/intel/common/block/include/intelblocks/sd.h create mode 100644 src/soc/intel/common/block/scs/Kconfig create mode 100644 src/soc/intel/common/block/scs/Makefile.inc create mode 100644 src/soc/intel/common/block/scs/sd.c (limited to 'src/soc') diff --git a/src/soc/intel/common/block/include/intelblocks/sd.h b/src/soc/intel/common/block/include/intelblocks/sd.h new file mode 100644 index 0000000000..1dde344572 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/sd.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_SD_H +#define SOC_INTEL_COMMON_BLOCK_SD_H + +#include + +/* + * Fill the GPIO Interrupt or I/O information that will be used for the + * GPIO Connection Descriptor. + */ +int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev); + +#endif /* SOC_INTEL_COMMON_BLOCK_SD_H */ diff --git a/src/soc/intel/common/block/scs/Kconfig b/src/soc/intel/common/block/scs/Kconfig new file mode 100644 index 0000000000..0a402137bc --- /dev/null +++ b/src/soc/intel/common/block/scs/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_SCS + bool + help + Intel Processor common storage and communication subsystem support diff --git a/src/soc/intel/common/block/scs/Makefile.inc b/src/soc/intel/common/block/scs/Makefile.inc new file mode 100644 index 0000000000..1c2a6c6692 --- /dev/null +++ b/src/soc/intel/common/block/scs/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += sd.c diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c new file mode 100644 index 0000000000..ec5f6e8cac --- /dev/null +++ b/src/soc/intel/common/block/scs/sd.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +static void sd_fill_ssdt(struct device *dev) +{ + const char *path; + struct acpi_gpio default_gpio = { 0 }; + struct acpi_dp *dp; + + if (!dev->enabled) + return; + + if (sd_fill_soc_gpio_info(&default_gpio, dev) != 0) + return; + + /* Use device path as the Scope for the SSDT */ + path = acpi_device_path(dev); + if (!path) + return; + acpigen_write_scope(path); + acpigen_write_name("_CRS"); + + /* Write GpioInt() as default (if set) or custom from devicetree */ + acpigen_write_resourcetemplate_header(); + acpi_device_write_gpio(&default_gpio); + acpigen_write_resourcetemplate_footer(); + + /* Bind the cd-gpio name to the GpioInt() resource */ + dp = acpi_dp_new_table("_DSD"); + if (!dp) + return; + acpi_dp_add_gpio(dp, "cd-gpio", path, 0, 0, 1); + acpi_dp_write(dp); + + acpigen_pop_len(); +} +#endif + +static struct device_operations dev_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = &sd_fill_ssdt, +#endif +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_APL_SD, + PCI_DEVICE_ID_INTEL_GLK_SD, + PCI_DEVICE_ID_INTEL_SKL_SD, + 0 +}; + +static const struct pci_driver pch_sd __pci_driver = { + .ops = &dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids +}; -- cgit v1.2.3