From 912616941930a352c27a841a735476998e804829 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Mon, 4 Mar 2019 15:43:47 +0100 Subject: soc/intel/braswell/include/soc/spi.h: Add OPTYPE values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add SPI_OPTYPE_XXX values for the SPI controller. BUG=N/A TEST=flashrom on Facebook FBG-1701 Change-Id: Id183d68b3a80b2e7ab1a0685580d79ca327db03a Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/31712 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Michał Żygowski --- src/soc/intel/braswell/include/soc/spi.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h index 49f3fcc0ac..2d275450fa 100644 --- a/src/soc/intel/braswell/include/soc/spi.h +++ b/src/soc/intel/braswell/include/soc/spi.h @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,6 +32,10 @@ # define DATA_CYCLE (0x1 << 14) #define PREOP 0x94 #define OPTYPE 0x96 +# define SPI_OPTYPE_RD_NOADDR 0x00 /* Read, no address */ +# define SPI_OPTYPE_WR_NOADDR 0x01 /* Write, no address */ +# define SPI_OPTYPE_RD_ADDR 0x02 /* Read, address required */ +# define SPI_OPTYPE_WR_ADDR 0x03 /* Write, address required */ #define OPMENU0 0x98 #define OPMENU1 0x9c #define LVSCC 0xc4 -- cgit v1.2.3