From 8d4e67da2046a5a6f55cd803c77b32d0c621cbc5 Mon Sep 17 00:00:00 2001 From: Lean Sheng Tan Date: Fri, 25 Jun 2021 11:23:03 -0700 Subject: soc/intel/elkhartlake: Expose FIVR config to mainboard Elkhart Lake provides option to configure FIVR (Fully Integrated Voltage Regulators) via parameters in FSP-S. This CL removes fixed FIVR config values and expose these parameters to the devicetree so that they can be configured on mainboard level as needed. Signed-off-by: Lean Sheng Tan Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55861 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Angel Pons --- src/soc/intel/elkhartlake/chip.h | 55 +++++++++++++++++++++++++++++++++- src/soc/intel/elkhartlake/fsp_params.c | 31 ++++++++++++------- 2 files changed, 75 insertions(+), 11 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index dbce712174..b4d5cc045e 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -48,6 +48,35 @@ enum tsn_gbe_link_speed { Tsn_1_Gbps, }; +/* + * Enable external V1P05 Rail in: BIT0:S0i1/S0i2, + * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5 + * However, EHL does not support S0i1 and S0i2, + * hence removed the option. + */ +enum fivr_states { + FIVR_ENABLE_S0i3 = BIT(1), + FIVR_ENABLE_S3 = BIT(2), + FIVR_ENABLE_S4 = BIT(3), + FIVR_ENABLE_S5 = BIT(4), + FIVR_ENABLE_S3_S4_S5 = FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5, + FIVR_ENABLE_ALL_SX = FIVR_ENABLE_S0i3 | FIVR_ENABLE_S3_S4_S5, +}; + +/* + * Enable the following for external V1p05 rail + * BIT1: Normal active voltage supported + * BIT2: Minimum active voltage supported + * BIT3: Minimum retention voltage supported + */ +enum fivr_supported_voltage { + FIVR_VOLTAGE_NORMAL = BIT(1), + FIVR_VOLTAGE_MIN_ACTIVE = BIT(2), + FIVR_VOLTAGE_MIN_RETENTION = BIT(3), + FIVR_ENABLE_ALL_VOLTAGE = FIVR_VOLTAGE_NORMAL | FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, +}; + struct soc_intel_elkhartlake_config { /* Common struct containing soc config data required by common code */ @@ -248,7 +277,7 @@ struct soc_intel_elkhartlake_config { * 1: High */ uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; -/* + /* * SerialIo I2C Pads Termination Config: * 0x0:Hardware default, * 0x1:None, @@ -348,6 +377,30 @@ struct soc_intel_elkhartlake_config { */ uint8_t SkipCpuReplacementCheck; + struct { + bool fivr_config_en; + enum fivr_states v1p05_state; + enum fivr_states vnn_state; + enum fivr_states vnn_sx_state; + enum fivr_supported_voltage v1p05_rail; + enum fivr_supported_voltage vnn_rail; + /* Icc max for V1p05 rail in mA */ + unsigned int v1p05_icc_max_ma; + /* Vnn voltage in mV */ + unsigned int vnn_sx_mv; + /* Transition time in microseconds: */ + /* From low current mode voltage to high current mode voltage */ + unsigned int vcc_low_high_us; + /* From retention mode voltage to high current mode voltage */ + unsigned int vcc_ret_high_us; + /* From retention mode voltage to low current mode voltage */ + unsigned int vcc_ret_low_us; + /* From off(0V) to high current mode voltage */ + unsigned int vcc_off_high_us; + /* RFI spread spectrum, in 0.1% increment. Range: 0.0% to 10.0% (0-100). */ + unsigned int spread_spectrum; + } fivr; + /* * SLP_S3 Minimum Assertion Width Policy * 1 = 60us diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index da9a783f42..31d987a568 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -59,6 +59,24 @@ static int get_l1_substate_control(enum L1_substates_control ctl) return ctl - 1; } +static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_elkhartlake_config *config) +{ + s_cfg->PchFivrExtV1p05RailEnabledStates = config->fivr.v1p05_state; + s_cfg->PchFivrExtV1p05RailSupportedVoltageStates = config->fivr.v1p05_rail; + s_cfg->PchFivrExtVnnRailEnabledStates = config->fivr.vnn_state; + s_cfg->PchFivrExtVnnRailSupportedVoltageStates = config->fivr.vnn_rail; + s_cfg->PchFivrExtVnnRailSxEnabledStates = config->fivr.vnn_sx_state; + s_cfg->PchFivrVccinAuxLowToHighCurModeVolTranTime = config->fivr.vcc_low_high_us; + s_cfg->PchFivrVccinAuxRetToHighCurModeVolTranTime = config->fivr.vcc_ret_high_us; + s_cfg->PchFivrVccinAuxRetToLowCurModeVolTranTime = config->fivr.vcc_ret_low_us; + s_cfg->PchFivrVccinAuxOffToHighCurModeVolTranTime = config->fivr.vcc_off_high_us; + /* Convert mV to number of 2.5 mV increments */ + s_cfg->PchFivrExtVnnRailSxVoltage = (config->fivr.vnn_sx_mv * 10) / 25; + s_cfg->PchFivrExtV1p05RailIccMaximum = config->fivr.v1p05_icc_max_ma; + s_cfg->FivrSpreadSpectrum = config->fivr.spread_spectrum; +} + static void parse_devicetree(FSP_S_CONFIG *params) { const struct soc_intel_elkhartlake_config *config = config_of_soc(); @@ -289,16 +307,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PmcV1p05PhyExtFetControlEn = 0x1; params->PmcV1p05IsExtFetControlEn = 0x1; /* FIVR config */ - params->PchFivrExtV1p05RailEnabledStates = 0x1E; - params->PchFivrExtV1p05RailSupportedVoltageStates = 0x2; - params->PchFivrExtVnnRailEnabledStates = 0x1E; - params->PchFivrExtVnnRailSupportedVoltageStates = 0xE; - params->PchFivrExtVnnRailSxEnabledStates = 0x1C; - params->PchFivrVccinAuxLowToHighCurModeVolTranTime = 0x0C; - params->PchFivrVccinAuxRetToHighCurModeVolTranTime = 0x36; - params->PchFivrVccinAuxRetToLowCurModeVolTranTime = 0x2B; - params->PchFivrVccinAuxOffToHighCurModeVolTranTime = 0x0096; - params->FivrSpreadSpectrum = 0xF; + if (config->fivr.fivr_config_en) { + fill_fsps_fivr_params(params, config); + } /* FuSa (Functional Safety) config */ if (!config->FuSaEnable) { -- cgit v1.2.3