From 84743a178a8c6ebd49bc1c08f35e9e6a69e84903 Mon Sep 17 00:00:00 2001
From: Aamir Bohra <aamir.bohra@intel.com>
Date: Wed, 3 Apr 2019 18:38:18 +0530
Subject: src/soc/intel/cannonlake: Remove ITSS IPC restore

Remove ITSS IPC restore for cannonlake, as it does not take effect
since the ITSS PCR registers are locked post FSP-S.

Change-Id: Ie39e0d43644cb7b03b6c3432f0965f1d76d1bc37
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/soc/intel/cannonlake/chip.c | 8 --------
 1 file changed, 8 deletions(-)

(limited to 'src/soc')

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index d50c6894d0..845e9ef34f 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -24,7 +24,6 @@
 #include <intelblocks/xdci.h>
 #include <romstage_handoff.h>
 #include <soc/intel/common/vbt.h>
-#include <soc/itss.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 
@@ -168,19 +167,12 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads)
 
 void soc_init_pre_device(void *chip_info)
 {
-	/* Snapshot the current GPIO IRQ polarities. FSP is setting a
-	 * default policy that doesn't honor boards' requirements. */
-	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
-
 	/* Perform silicon specific init. */
 	fsp_silicon_init(romstage_handoff_is_resume());
 
 	 /* Display FIRMWARE_VERSION_INFO_HOB */
 	fsp_display_fvi_version_hob();
 
-	/* Restore GPIO IRQ polarities back to previous settings. */
-	itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
-
 	/* TODO(furquan): Get rid of this workaround once FSP is fixed. */
 	cnl_configure_pads(NULL, 0);
 }
-- 
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