From 81096041b8da42b17e57c63bdf81902b6ec69d61 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 2 May 2017 18:54:44 -0700 Subject: soc/intel/cannonlake: Add initial dummy directory Add Cannon Lake SoC boilerplate directory with: * SoC directory * Base Kconfig * Dummy cbmem.c Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Signed-off-by: Lijian Zhao Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/20061 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/Kconfig | 67 +++++++++++++++++++++++++++++++++++ src/soc/intel/cannonlake/Makefile.inc | 7 ++++ src/soc/intel/cannonlake/cbmem.c | 22 ++++++++++++ 3 files changed, 96 insertions(+) create mode 100644 src/soc/intel/cannonlake/Kconfig create mode 100644 src/soc/intel/cannonlake/Makefile.inc create mode 100644 src/soc/intel/cannonlake/cbmem.c (limited to 'src/soc') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig new file mode 100644 index 0000000000..5da39b961f --- /dev/null +++ b/src/soc/intel/cannonlake/Kconfig @@ -0,0 +1,67 @@ +config SOC_INTEL_CANNONLAKE + bool + help + Intel Cannonlake support + +if SOC_INTEL_CANNONLAKE + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select HAVE_MONOTONIC_TIMER + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select REG_SCRIPT + select C_ENVIRONMENT_BOOTBLOCK + select HAVE_HARD_RESET + select HAVE_INTEL_FIRMWARE + select INTEL_CAR_NEM_ENHANCED + select PLATFORM_USES_FSP2_0 + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_LPSS + select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_BLOCK_FAST_SPI + select SOC_INTEL_COMMON_BLOCK_PCR + select SOC_INTEL_COMMON_BLOCK_SMBUS + select SOC_INTEL_COMMON_BLOCK_RTC + select SOC_INTEL_COMMON_BLOCK_CSE + +config UART_DEBUG + bool "Enable UART debug port." + default y + select CONSOLE_SERIAL + select BOOTBLOCK_CONSOLE + select DRIVERS_UART + select DRIVERS_UART_8250IO + +config DCACHE_RAM_BASE + default 0xfef00000 + +config DCACHE_RAM_SIZE + default 0x40000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +endif diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc new file mode 100644 index 0000000000..4651a23862 --- /dev/null +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -0,0 +1,7 @@ +ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y) + +romstage-y += cbmem.c + +ramstage-y += cbmem.c + +endif diff --git a/src/soc/intel/cannonlake/cbmem.c b/src/soc/intel/cannonlake/cbmem.c new file mode 100644 index 0000000000..0f47173061 --- /dev/null +++ b/src/soc/intel/cannonlake/cbmem.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +void *cbmem_top(void) +{ + /* not implemented yet */ + return (void *) NULL; +} -- cgit v1.2.3