From 7f72c9b30ec543fc5d485dca5f15790d2c4b03f3 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Fri, 24 Jun 2016 18:15:09 -0700 Subject: soc/intel/apollolake: Update stage link addresses for 768 KiB cache Update link addresses for romstage and verstage. Also update FSP-M relocation address. BUG=chrome-os-partner:51959 Change-Id: Ia51a341f05b33151ea5fda9f8620408b5a15bc19 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/15454 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a92a05281d..d8e33caf7b 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -145,13 +145,13 @@ config X86_TOP4G_BOOTMEDIA_MAP config ROMSTAGE_ADDR hex - default 0xfef3e000 + default 0xfef20000 help The base address (in CAR) where romstage should be linked config VERSTAGE_ADDR hex - default 0xfef60000 + default 0xfef40000 help The base address (in CAR) where verstage should be linked @@ -161,7 +161,7 @@ config CACHE_MRC_SETTINGS config FSP_M_ADDR hex - default 0xfef60000 + default 0xfef40000 help The address FSP-M will be relocated to during build time -- cgit v1.2.3