From 7d054bd38f5cfe36f6abd4f4422c463243bc3749 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 19 May 2020 11:10:21 -0700 Subject: soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method CPU to PCH method refers to PCH ACPI operation region which was wrongly defined as SystemMemory and PCH_PWRM_BASE_ADDRESS. Change the operation region to be SystemIO and ACPI_BASE_ADDRESS. BUG=b:156530805 TEST=Built and booted to kernel. Signed-off-by: John zhao Change-Id: Ifa291a993ec23e1e4dfad8f6cdfabc80b824d20c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41537 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/tigerlake/acpi/tcss.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 7d586dd11e..abdcb515fa 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -45,10 +45,10 @@ Scope (\_SB) } /* - * Define PCH ACPIBASE as an ACPI operating region. The base address can be + * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be * found in Device 31, Function 2, Offset 40h. */ - OperationRegion (PMIO, SystemMemory, PCH_PWRM_BASE_ADDRESS, 0x80) + OperationRegion (PMIO, SystemIO, ACPI_BASE_ADDRESS, 0x80) Field (PMIO, ByteAcc, NoLock, Preserve) { Offset(0x6C), /* 0x6C, General Purpose Event 0 Status [127:96] */ , 19, -- cgit v1.2.3