From 7c8de869a2e6d684776d31b51c022c01287ebc12 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 7 Jan 2021 16:47:23 +0100 Subject: soc/intel/cannonlake: Enable wake from USB in S4 The xHCI controller supports waking the system from S1-S4. Thus specify that the deepest sleep state is S4 in _PRW. Tested on Prodrive/hermes. The board now wakes from S4 as well by pressing a key on the USB keyboard. Change-Id: I0bb266e70ee6b4eb8922671b7d0078db0d29a1da Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/49224 Reviewed-by: Christian Walter Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/acpi/xhci.asl | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/soc') diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl index 7d89665dca..50c0cb8a0c 100644 --- a/src/soc/intel/cannonlake/acpi/xhci.asl +++ b/src/soc/intel/cannonlake/acpi/xhci.asl @@ -67,7 +67,7 @@ Device (XHCI) { Name (_ADR, 0x00140000) - Name (_PRW, Package () { GPE0_PME_B0, 3 }) + Name (_PRW, Package () { GPE0_PME_B0, 4 }) Method (_DSW, 3) { @@ -79,6 +79,9 @@ Device (XHCI) Name (_S0W, 3) /* D3 can wake device in S0 */ Name (_S3W, 3) /* D3 can wake system from S3 */ + Name (_S4D, 3) /* D3 supported in S4 */ + Name (_S4W, 3) /* D3 can wake system from S4 */ + OperationRegion (XPRT, PCI_Config, 0x00, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { -- cgit v1.2.3