From 7c477a9d1afe324050da6185ab3d22271c94fd7b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 14 Mar 2022 12:47:31 +0530 Subject: soc/intel/common/block/p2sb: Add helper function to enable BAR This patch creates a new helper function to enable P2SB BAR. `p2sb_dev_enable_bar()` takes the PCI P2SB device address (B/D/F) and BAR address (combining high and low base addresses). BUG=b:224325352 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62778 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Tim Wawrzynczak Reviewed-by: Felix Held Reviewed-by: Wonkyu Kim --- src/soc/intel/common/block/include/intelblocks/p2sblib.h | 1 + src/soc/intel/common/block/p2sb/Makefile.inc | 2 ++ src/soc/intel/common/block/p2sb/p2sb.c | 8 +------- src/soc/intel/common/block/p2sb/p2sblib.c | 10 ++++++++++ 4 files changed, 14 insertions(+), 7 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/common/block/include/intelblocks/p2sblib.h b/src/soc/intel/common/block/include/intelblocks/p2sblib.h index 7df528d20d..9f6b97d6e2 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sblib.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sblib.h @@ -10,6 +10,7 @@ #define P2SBC 0xe0 #define P2SBC_HIDE_BIT (1 << 0) +void p2sb_dev_enable_bar(pci_devfn_t dev, uint64_t bar); bool p2sb_dev_is_hidden(pci_devfn_t dev); void p2sb_dev_unhide(pci_devfn_t dev); void p2sb_dev_hide(pci_devfn_t dev); diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc index dbf45452a2..f05112014b 100644 --- a/src/soc/intel/common/block/p2sb/Makefile.inc +++ b/src/soc/intel/common/block/p2sb/Makefile.inc @@ -1,3 +1,5 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 94db33d2fe..1b0c080913 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -18,13 +18,7 @@ void p2sb_enable_bar(void) { - /* Enable PCR Base address in PCH */ - pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, P2SB_BAR); - pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); - - /* Enable P2SB MSE */ - pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + p2sb_dev_enable_bar(PCH_DEV_P2SB, P2SB_BAR); } /* diff --git a/src/soc/intel/common/block/p2sb/p2sblib.c b/src/soc/intel/common/block/p2sb/p2sblib.c index faef79adfd..e1a5bc2ef8 100644 --- a/src/soc/intel/common/block/p2sb/p2sblib.c +++ b/src/soc/intel/common/block/p2sb/p2sblib.c @@ -10,6 +10,16 @@ #include #include +void p2sb_dev_enable_bar(pci_devfn_t dev, uint64_t bar) +{ + /* Enable PCR Base addresses */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, (uint32_t)bar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, (uint32_t)(bar >> 32)); + + /* Enable P2SB MSE */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); +} + bool p2sb_dev_is_hidden(pci_devfn_t dev) { const uint16_t pci_vid = pci_read_config16(dev, PCI_VENDOR_ID); -- cgit v1.2.3