From 7bf860ffedb10a5d69381ad92b3eb7a1169969a9 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 27 Jul 2017 09:05:44 -0600 Subject: soc/amd/stoneyridge: Clarify BAR mask in SPI base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The format of the D14F3xA0 SPI Base_Addr register is different than a traditional BAR. Change the function to preserve any enables already in place. Change the AND mask to remove the reserved field and the enables. Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/20790 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Kyösti Mälkki Reviewed-by: Martin Roth Reviewed-by: Paul Menzel --- src/soc/amd/stoneyridge/early_setup.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index 68bccc4456..ca3447f6a7 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -242,13 +242,16 @@ static uintptr_t hudson_spibase(void) { /* Make sure the base address is predictable */ device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); + u32 base, enables; + + base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); + enables = base & 0xf; + base &= ~0x3f; - u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) - & 0xfffffff0; if (!base) { base = SPI_BASE_ADDRESS; pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base - | SPI_ROM_ENABLE); + | enables | SPI_ROM_ENABLE); /* PCI_COMMAND_MEMORY is read-only and enabled. */ } return (uintptr_t)base; -- cgit v1.2.3