From 79ccc6933284ca02d17d9e1eda9a531ce43e1f65 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 24 Feb 2020 13:43:39 +0100 Subject: src: capitalize 'PCIe' Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/acpi/globalnvs.asl | 2 +- src/soc/intel/baytrail/include/soc/nvs.h | 2 +- src/soc/intel/baytrail/pcie.c | 2 +- src/soc/intel/braswell/acpi/globalnvs.asl | 2 +- src/soc/intel/braswell/include/soc/nvs.h | 2 +- src/soc/intel/broadwell/acpi/globalnvs.asl | 2 +- src/soc/intel/broadwell/include/soc/nvs.h | 2 +- src/soc/intel/cannonlake/chip.h | 2 +- src/soc/intel/denverton_ns/smm.c | 2 +- src/soc/intel/icelake/chip.h | 2 +- src/soc/intel/skylake/acpi/globalnvs.asl | 2 +- src/soc/intel/skylake/chip.h | 2 +- src/soc/intel/skylake/include/soc/nvs.h | 2 +- src/soc/intel/tigerlake/chip.h | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 703e20fa8a..a8b0f53719 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -99,7 +99,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 4a89eb967e..8532728503 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -83,7 +83,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 6dc0346b23..6b6c28d731 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -163,7 +163,7 @@ static u8 all_ports_no_dev_present(struct device *dev) dev->path.pci.devfn &= ~0x7; dev->path.pci.devfn |= func; - /* is pcie device there */ + /* is PCIe device there */ if (pci_read_config32(dev, 0) == 0xFFFFFFFF) continue; diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index a67117da5f..41f1854d30 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -101,7 +101,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 33800ef8fd..f4cd8f2444 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -86,7 +86,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index 22a22e3ed1..87c053bc2a 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -91,7 +91,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 456fda6fa6..ea64341e58 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -75,7 +75,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd2; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 752ec1f315..330555c0c0 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -180,7 +180,7 @@ struct soc_intel_cannonlake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index d05e76bcf9..75f179ec67 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -53,7 +53,7 @@ void smm_southbridge_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); - /* Configure events Disable pcie wake. */ + /* Configure events Disable PCIe wake. */ enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); disable_gpe(PME_B0_EN); diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 569160f41f..56f89db5e7 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -134,7 +134,7 @@ struct soc_intel_icelake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index e17b2604cf..8aeb5a37f0 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -106,7 +106,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index b189a16a05..2c3d3a59c8 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -226,7 +226,7 @@ struct soc_intel_skylake_config { u8 PchDciEn; /* - * Pcie Root Port configuration: + * PCIe Root Port configuration: * each element of array corresponds to * respective PCIe root port. */ diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index d5f62f63fc..24e4cf1a2a 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -88,7 +88,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 9eee97d53b..e57abe857b 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -114,7 +114,7 @@ struct soc_intel_tigerlake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; -- cgit v1.2.3