From 7952e283fb6dac19a10112199814c80619a28366 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 14 Mar 2017 18:26:27 +0530 Subject: soc/intel/apollolake: Clean up code by using common System Agent module This patch currently contains the SA initialization required for bootblock phase - 1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code. 2. Perform PCIEXBAR programming based on soc configurable PCIEX_LENGTH_xxxMB 3. Use common systemagent header file. Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad Signed-off-by: Barnali Sarkar Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/18567 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Kconfig | 8 ++--- src/soc/intel/apollolake/bootblock/bootblock.c | 16 +++------ src/soc/intel/apollolake/chip.c | 2 +- src/soc/intel/apollolake/include/soc/northbridge.h | 40 ---------------------- src/soc/intel/apollolake/include/soc/systemagent.h | 32 +++++++++++++++++ src/soc/intel/apollolake/memmap.c | 2 +- src/soc/intel/apollolake/northbridge.c | 4 +-- src/soc/intel/apollolake/romstage.c | 2 +- 8 files changed, 45 insertions(+), 61 deletions(-) delete mode 100644 src/soc/intel/apollolake/include/soc/northbridge.h create mode 100644 src/soc/intel/apollolake/include/soc/systemagent.h (limited to 'src/soc') diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 5087fa6033..9b847da1d9 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE + select PCIEX_LENGTH_256MB select POSTCAR_CONSOLE select POSTCAR_STAGE select REG_SCRIPT @@ -51,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_SMI select SOC_INTEL_COMMON_SPI_FLASH_PROTECT @@ -89,10 +91,6 @@ config SOC_INTEL_COMMON_RESET bool default y -config MMCONF_BASE_ADDRESS - hex "PCI MMIO Base Address" - default 0xe0000000 - config IOSF_BASE_ADDRESS hex "MMIO Base Address of sideband bus" default 0xd0000000 @@ -283,7 +281,7 @@ config USE_APOLLOLAKE_FSP_CAR bool "Use FSP CAR" select FSP_CAR help - Use FSP APIs to initialize & tear Down the Cache-As-Ram. + Use FSP APIs to initialize & tear down the Cache-As-Ram. endchoice diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index ed4530ce76..dc17b15ad7 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -25,7 +26,7 @@ #include #include #include -#include +#include #include #include #include @@ -51,16 +52,9 @@ static void enable_cmos_upper_bank(void) asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - device_t dev = SA_DEV_ROOT; - - /* Set PCI Express BAR */ - pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1); - /* - * Clear TSEG register - TSEG register comes out of reset with a - * non-zero default value. Clear this register to ensure that there are - * no surprises in CBMEM handling. - */ - pci_write_config32(dev, TSEG, 0); + device_t dev; + + bootblock_systemagent_early_init(); dev = PCH_DEV_P2SB; /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */ diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 71706d047b..8aed7b68aa 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include "chip.h" diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h deleted file mode 100644 index 04e369e7e8..0000000000 --- a/src/soc/intel/apollolake/include/soc/northbridge.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corp. - * (Written by Andrey Petrov for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_ -#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_ - -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define PCIEX_SIZE (256 * MiB) - -#define BDSM 0xb0 /* Base Data Stolen Memory */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEG 0xb8 /* TSEG base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ - -/* IMR registers are found under MCHBAR. */ -#define MCHBAR_IMR0BASE 0x6870 -#define MCHBAR_IMR0MASK 0x6874 -#define MCH_IMR_PITCH 0x20 -#define MCH_NUM_IMRS 20 - -/* RAPL Package Power Limit register under MCHBAR. */ -#define MCHBAR_RAPL_PPL 0x70A8 - -#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/systemagent.h b/src/soc/intel/apollolake/include/soc/systemagent.h new file mode 100644 index 0000000000..9944c15197 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/systemagent.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_APOLLOLAKE_SYSTEMAGENT_H +#define SOC_APOLLOLAKE_SYSTEMAGENT_H + +#include + +/* IMR registers are found under MCHBAR. */ +#define MCHBAR_IMR0BASE 0x6870 +#define MCHBAR_IMR0MASK 0x6874 +#define MCH_IMR_PITCH 0x20 +#define MCH_NUM_IMRS 20 + +/* RAPL Package Power Limit register under MCHBAR. */ +#define MCHBAR_RAPL_PPL 0x70A8 + +#endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */ diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index a10477c305..0f85b10aab 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c index 6f92283c43..9519603300 100644 --- a/src/soc/intel/apollolake/northbridge.c +++ b/src/soc/intel/apollolake/northbridge.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include static uint32_t get_bar(device_t dev, unsigned int index) @@ -39,7 +39,7 @@ static int mc_add_fixed_mmio_resources(device_t dev, int index) /* PCI extended config region */ addr = ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB) / KiB; - mmio_resource(dev, index++, addr, PCIEX_SIZE / KiB); + mmio_resource(dev, index++, addr, CONFIG_SA_PCIEX_LENGTH / KiB); /* Memory Controller Hub */ addr = ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB) / KiB; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 38cf81cdc5..0270920c95 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include #include -- cgit v1.2.3