From 759bb4c00d818011c754e62afbe554b6a4cb52d4 Mon Sep 17 00:00:00 2001 From: Franklin Lin Date: Fri, 15 Jul 2022 17:53:13 +0800 Subject: soc/intel/alderlake/fsp_params.c: Set DdrSpeedControl UPD When override "max_dram_speed_mts", set the DdrSpeedControl to manual. (0:Auto, 1:Manual) BUG=b:229549930 BRANCH=none TEST=build coreboot without error Signed-off-by: Franklin Lin Change-Id: Iffbbee8082fb1a41e0ed1db3f4ea9ec4709c9ce7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65877 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/romstage/fsp_params.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/soc') diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 4e58c29008..337c4a609b 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -150,8 +150,10 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, { m_cfg->SaGv = config->sagv; m_cfg->RMT = config->RMT; - if (config->max_dram_speed_mts) + if (config->max_dram_speed_mts) { m_cfg->DdrFreqLimit = config->max_dram_speed_mts; + m_cfg->DdrSpeedControl = 1; + } } static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, -- cgit v1.2.3