From 716320b726a4fa6e7f42f2aec90de6f98ef52dd3 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Tue, 10 Aug 2021 12:28:09 +0800 Subject: soc/mediatek/mt8192: move DFD driver to common folder Move DFD driver to common folder so MT8195 can also use it. BUG=b:192429713 TEST=emerge-asurada coreboot Signed-off-by: Rex-BC Chen Change-Id: I7937cddf5f3a66f9269a94301d3134e6f4f9f22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56908 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/common/Kconfig | 6 ++++++ src/soc/mediatek/common/dfd.c | 12 ++++++++++++ src/soc/mediatek/common/include/soc/dfd_common.h | 13 +++++++++++++ src/soc/mediatek/mt8192/Kconfig | 6 ------ src/soc/mediatek/mt8192/Makefile.inc | 2 +- src/soc/mediatek/mt8192/dfd.c | 12 ------------ src/soc/mediatek/mt8192/include/soc/dfd.h | 7 +------ 7 files changed, 33 insertions(+), 25 deletions(-) create mode 100644 src/soc/mediatek/common/dfd.c create mode 100644 src/soc/mediatek/common/include/soc/dfd_common.h delete mode 100644 src/soc/mediatek/mt8192/dfd.c (limited to 'src/soc') diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index ab24617d86..754c0da580 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -40,4 +40,10 @@ config DPM_FOUR_CHANNEL help This option enables four channel configuration for DPM. +config MTK_DFD + bool + default n + help + This option enables DFD (Design for Debug) settings. + endif diff --git a/src/soc/mediatek/common/dfd.c b/src/soc/mediatek/common/dfd.c new file mode 100644 index 0000000000..103151f377 --- /dev/null +++ b/src/soc/mediatek/common/dfd.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void dfd_init(void) +{ + printk(BIOS_INFO, "%s: enable DFD (Design For Debug)\n", __func__); + setbits32(dfd_cfg, RESET_ON_KEEP_EN); + dsb(); +} diff --git a/src/soc/mediatek/common/include/soc/dfd_common.h b/src/soc/mediatek/common/include/soc/dfd_common.h new file mode 100644 index 0000000000..d716ed0823 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dfd_common.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_DFD_COMMON_H +#define SOC_MEDIATEK_DFD_COMMON_H + +#define CPC_FLOW_CTRL_CFG 0x0C53A814 +#define RESET_ON_KEEP_EN BIT(17) + +static u32 *const dfd_cfg = (void *)CPC_FLOW_CTRL_CFG; + +void dfd_init(void); + +#endif diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index 94e4bd3d14..e099ffdf0f 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -64,10 +64,4 @@ config SRCLKEN_RC_SUPPORT This option enables clock buffer remote controller module to control PMIC 26MHz clock output. -config MTK_DFD - bool - default n - help - This option enables DFD (Design for Debug) settings. - endif diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 5bd88c32a4..934b6888b2 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -46,7 +46,7 @@ ramstage-y += apusys.c ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c -ramstage-y += dfd.c +ramstage-y += ../common/dfd.c ramstage-y += ../common/dpm.c ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += ../common/flash_controller.c diff --git a/src/soc/mediatek/mt8192/dfd.c b/src/soc/mediatek/mt8192/dfd.c deleted file mode 100644 index 4d1b08aab4..0000000000 --- a/src/soc/mediatek/mt8192/dfd.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -void dfd_init(void) -{ - printk(BIOS_INFO, "[%s]\n", __func__); - setbits32(dfd_cfg, RESET_ON_KEEP_EN); - dsb(); -} diff --git a/src/soc/mediatek/mt8192/include/soc/dfd.h b/src/soc/mediatek/mt8192/include/soc/dfd.h index 650e5fd091..e225b08060 100644 --- a/src/soc/mediatek/mt8192/include/soc/dfd.h +++ b/src/soc/mediatek/mt8192/include/soc/dfd.h @@ -3,15 +3,10 @@ #ifndef SOC_MEDIATEK_MT8192_DFD_H #define SOC_MEDIATEK_MT8192_DFD_H -#define CPC_FLOW_CTRL_CFG 0x0C53A814 -#define RESET_ON_KEEP_EN BIT(17) +#include /* DFD dump address and size need to be the same as defined in Kernel DTS. */ #define DFD_DUMP_ADDRESS 0x6A000000 #define DFD_DUMP_SIZE (1 * MiB) -static u32 *const dfd_cfg = (void *)CPC_FLOW_CTRL_CFG; - -void dfd_init(void); - #endif -- cgit v1.2.3