From 6fcee7533c1a4036224339ae299e448e210ca78d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Sun, 14 Feb 2021 15:06:50 +0200
Subject: soc/intel/denverton_ns: Sanity check MMCONF_BASE_ADDRESS
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

According to received feedback, FSP-T enables MMCONF at address
0xe0000000 with 256 busses. Sanity-check that Kconfig matches that.

Add MMCONF_BUS_NUMBER such that MCFG in ACPI will be correct.

Change-Id: I01309638a9f4ada71e5e3789db34892ed4abfa3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/denverton_ns/Kconfig               |  4 +++
 src/soc/intel/denverton_ns/acpi.c                | 17 +++---------
 src/soc/intel/denverton_ns/acpi/northcluster.asl |  2 +-
 src/soc/intel/denverton_ns/bootblock/bootblock.c | 34 +++++++++++++++++++++++-
 4 files changed, 42 insertions(+), 15 deletions(-)

(limited to 'src/soc')

diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index bfd8c3f736..e8e563c317 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -47,6 +47,10 @@ config CPU_SPECIFIC_OPTIONS
 config MMCONF_BASE_ADDRESS
 	default 0xe0000000
 
+config MMCONF_BUS_NUMBER
+	int
+	default 256
+
 config FSP_HEADER_PATH
 	default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/"
 
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c
index 569e61d9de..921cbc9cf6 100644
--- a/src/soc/intel/denverton_ns/acpi.c
+++ b/src/soc/intel/denverton_ns/acpi.c
@@ -83,19 +83,10 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
-	u32 pciexbar_reg;
-	int max_buses;
-
-	pciexbar_reg = get_pciebase();
-	max_buses = get_pcielength();
-
-	if (!pciexbar_reg)
-		return current;
-
-	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
-					     pciexbar_reg, 0x0, 0x0,
-					     (u8)(max_buses - 1));
-
+	/* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
+	current += acpi_create_mcfg_mmconfig((void *)current,
+					     CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
+					     CONFIG_MMCONF_BUS_NUMBER - 1);
 	return current;
 }
 
diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl
index 40d745ef62..26a6f2ed95 100644
--- a/src/soc/intel/denverton_ns/acpi/northcluster.asl
+++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl
@@ -122,7 +122,7 @@ Device (PDRC)
 
 	Name (PDRS, ResourceTemplate() {
 		// PCIEXBAR memory range
-		Memory32Fixed(ReadOnly, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000)
+		Memory32Fixed(ReadOnly, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
 		// TSEG
 		Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB)
 	})
diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c
index 76db62e3fd..1aebab4f83 100644
--- a/src/soc/intel/denverton_ns/bootblock/bootblock.c
+++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c
@@ -1,12 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <assert.h>
 #include <bootblock_common.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <FsptUpd.h>
 #include <intelblocks/fast_spi.h>
 #include <soc/bootblock.h>
-#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/systemagent.h>
 #include <spi-generic.h>
+#include <stdint.h>
 #include <console/console.h>
 
 const FSPT_UPD temp_ram_init_params = {
@@ -48,6 +52,32 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 	bootblock_main_with_basetime(base_timestamp);
 };
 
+static void sanity_check_pci_mmconf(void)
+{
+	u32 pciexbar, base = 0, length = 0;
+
+	pciexbar = pci_io_read_config32(PCH_SA_DEV, PCIEXBAR);
+	assert(pciexbar & (1 << 0));
+
+	switch (pciexbar & MASK_PCIEXBAR_LENGTH) {
+	case MASK_PCIEXBAR_LENGTH_256M:
+		base = pciexbar & MASK_PCIEXBAR_256M;
+		length = 256;
+		break;
+	case MASK_PCIEXBAR_LENGTH_128M:
+		base = pciexbar & MASK_PCIEXBAR_128M;
+		length = 128;
+		break;
+	case MASK_PCIEXBAR_LENGTH_64M:
+		base = pciexbar & MASK_PCIEXBAR_64M;
+		length = 64;
+		break;
+	}
+
+	assert(base == CONFIG_MMCONF_BASE_ADDRESS);
+	assert(length == CONFIG_MMCONF_BUS_NUMBER);
+}
+
 void bootblock_soc_early_init(void)
 {
 
@@ -58,6 +88,8 @@ void bootblock_soc_early_init(void)
 
 void bootblock_soc_init(void)
 {
+	sanity_check_pci_mmconf();
+
 	if (CONFIG(BOOTBLOCK_CONSOLE))
 		printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");
 };
-- 
cgit v1.2.3