From 6e3379784120a16a2f865c545404d0deb4074322 Mon Sep 17 00:00:00 2001
From: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Date: Tue, 17 Dec 2019 00:05:44 -0800
Subject: soc/intel/tigerlake: Fix PMC config

Fix PMC base address for tigerlake.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Id13222eb5498a5704c11d6b4d1e83212bd8b2723
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
---
 src/soc/intel/tigerlake/bootblock/pch.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/soc')

diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 7a93182661..1654809a6b 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -40,7 +40,7 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 
-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP	0x0600
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP	0x1100
 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP	0x0980
 #define PCR_PSFX_TO_SHDW_BAR0	0
 #define PCR_PSFX_TO_SHDW_BAR1	0x4
-- 
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