From 6caa4769c763b10a440637ce9c8d11ef1764c90d Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Thu, 18 Jun 2020 16:50:58 +0530 Subject: tigerlake: enable tcc_offset functionality This enables Thermal Control Circuit (TCC) activation feature to set tcc_offset to new value in devicetree. BUG=None BRANCH=None TEST=Built for volteer platform and verified the MSR value. Change-Id: I36b0d6aad4be8a9cbb145dcd66d65235d3f6ac35 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/42513 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/cpu.c | 3 +++ src/soc/intel/tigerlake/fsp_params.c | 3 +++ 2 files changed, 6 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index ec78d15616..9a96f8f7cd 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -216,4 +216,7 @@ void soc_init_cpus(struct bus *cpu_bus) { if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); + + /* Thermal throttle activation offset */ + configure_tcc_thermal_target(); } diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 3fbb89a793..a612427418 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -213,6 +213,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable TCPU for processor thermal control */ params->Device4Enable = config->Device4Enable; + /* Set TccActivationOffset */ + params->TccActivationOffset = config->tcc_offset; + /* LAN */ dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) -- cgit v1.2.3