From 6bb0f8aaa489e5f8da2818069623bc2f202a42ef Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 13 Nov 2023 20:57:12 -0600 Subject: soc/amd/common: Move PCIe CLKREQ programming under fsp CLKREQ programming as currently implemented is completely dependent on FSP DXIO descriptors, so move under common/fsp/pci and rename the Kconfig to reflect the move. TEST=build google/{guybrush, skyrim, myst} Change-Id: I87b53d092ddc367b134c25949f9da7670a6a1d88 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/79016 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Nico Huber Reviewed-by: Martin L Roth --- src/soc/amd/cezanne/Kconfig | 2 +- src/soc/amd/common/block/pci/Kconfig | 7 --- src/soc/amd/common/block/pci/Makefile.inc | 1 - src/soc/amd/common/block/pci/pcie_clk_req.c | 96 ----------------------------- src/soc/amd/common/fsp/pci/Kconfig | 7 +++ src/soc/amd/common/fsp/pci/Makefile.inc | 5 +- src/soc/amd/common/fsp/pci/pcie_clk_req.c | 96 +++++++++++++++++++++++++++++ src/soc/amd/mendocino/Kconfig | 2 +- src/soc/amd/phoenix/Kconfig | 2 +- 9 files changed, 108 insertions(+), 110 deletions(-) delete mode 100644 src/soc/amd/common/block/pci/pcie_clk_req.c create mode 100644 src/soc/amd/common/fsp/pci/pcie_clk_req.c (limited to 'src/soc') diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 3700f18772..9c15dd9894 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -55,7 +55,6 @@ config SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER - select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 @@ -74,6 +73,7 @@ config SOC_AMD_CEZANNE select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI + select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SOC_AMD_COMMON_BLOCK_XHCI select SSE2 diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig index 1c21833bd2..302a6b8497 100644 --- a/src/soc/amd/common/block/pci/Kconfig +++ b/src/soc/amd/common/block/pci/Kconfig @@ -16,10 +16,3 @@ config SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER depends on SOC_AMD_COMMON_BLOCK_PCI help Select this option to use AMD common PCIe GPP driver. - -config SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ - bool - depends on SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER - help - This option includes code to disable PCIe clock request if the corresponding - PCIe device is disabled. diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 372c6ce411..ece43cb67e 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -5,7 +5,6 @@ ramstage-y += amd_pci_util.c ramstage-y += pci_routing_info.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER) += pcie_gpp.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ) += pcie_clk_req.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI diff --git a/src/soc/amd/common/block/pci/pcie_clk_req.c b/src/soc/amd/common/block/pci/pcie_clk_req.c deleted file mode 100644 index 881c650ed4..0000000000 --- a/src/soc/amd/common/block/pci/pcie_clk_req.c +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include -#include -#include - -/* Update gpp glk req config based on DXIO descriptors and enabled devices. */ -void pcie_gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config, - size_t gpp_clk_config_num) -{ - const fsp_dxio_descriptor *dxio_descs = NULL; - const fsp_ddi_descriptor *ddi_descs = NULL; - size_t dxio_num = 0; - size_t ddi_num = 0; - - mainboard_get_dxio_ddi_descriptors(&dxio_descs, &dxio_num, &ddi_descs, &ddi_num); - if (dxio_descs == NULL) { - printk(BIOS_WARNING, - "No DXIO descriptors found, GPP clk req may not reflect enabled devices\n"); - return; - } - - for (int i = 0; i < dxio_num; i++) { - const fsp_dxio_descriptor *dxio_desc = &dxio_descs[i]; - - /* Only consider PCIe and unused engine types. */ - if (dxio_desc->engine_type != PCIE_ENGINE - && dxio_desc->engine_type != UNUSED_ENGINE) - continue; - enum cpm_clk_req dxio_clk_req = dxio_desc->clk_req; - - /* CLK_DISABLE means there's no corresponding clk req line in use */ - if (dxio_clk_req == CLK_DISABLE) - continue; - - /* - * dxio_clk_req is only 4 bits so having CLK_ENABLE as a value for - * a descriptor should cause a compiler error. 0xF isn't a - * valid clk_req value according to AMD's internal code either. - * This is here to draw attention in case this code is ever used - * in a situation where this has changed. - */ - if (dxio_clk_req == (CLK_ENABLE & 0xF)) { - printk(BIOS_WARNING, - "CLK_ENABLE is an invalid clk_req value for PCIe device %d.%d, DXIO descriptor %d\n", - dxio_desc->device_number, dxio_desc->function_number, i); - continue; - } - - /* cpm_clk_req 0 is CLK_DISABLE */ - int gpp_req_index = dxio_clk_req - CLK_REQ0; - /* Ensure that our index is valid */ - if (gpp_req_index < 0 || gpp_req_index >= gpp_clk_config_num) { - printk(BIOS_ERR, - "Failed to convert DXIO clk req value %d to GPP clk req index for PCIe device %d.%d, DXIO descriptor %d, clk req settings may be incorrect\n", - dxio_clk_req, dxio_desc->device_number, - dxio_desc->function_number, i); - continue; - } - - const struct device *pci_device = pcidev_path_on_root( - PCI_DEVFN(dxio_desc->device_number, dxio_desc->function_number)); - if (pci_device == NULL) { - gpp_clk_config[gpp_req_index] = GPP_CLK_OFF; - printk(BIOS_WARNING, - "Cannot find PCIe device %d.%d, disabling GPP clk req %d, DXIO descriptor %d\n", - dxio_desc->device_number, dxio_desc->function_number, i, - gpp_req_index); - continue; - } - - /* PCIe devices haven't been fully set up yet, so directly read the vendor id - * and device id to determine if a device is physically present. If a device - * is not present then the id should be 0xffffffff. 0x00000000, 0xffff0000, - * and 0x0000ffff are there to account for any odd failure cases. */ - u32 id = pci_read_config32(pci_device, PCI_VENDOR_ID); - bool enabled = pci_device->enabled && (id != 0xffffffff) && (id != 0x00000000) - && (id != 0x0000ffff) && (id != 0xffff0000); - - /* Inform of possible mismatches between devices and SoC gpp_clk_config. */ - if (!enabled && gpp_clk_config[gpp_req_index] != GPP_CLK_OFF) { - gpp_clk_config[gpp_req_index] = GPP_CLK_OFF; - printk(BIOS_INFO, - "PCIe device %d.%d disabled, disabling GPP clk req %d, DXIO descriptor %d\n", - dxio_desc->device_number, dxio_desc->function_number, - gpp_req_index, i); - } else if (enabled && gpp_clk_config[gpp_req_index] == GPP_CLK_OFF) { - printk(BIOS_INFO, - "PCIe device %d.%d enabled, GPP clk req is off, DXIO descriptor %d\n", - dxio_desc->device_number, dxio_desc->function_number, i); - } - } -} diff --git a/src/soc/amd/common/fsp/pci/Kconfig b/src/soc/amd/common/fsp/pci/Kconfig index 9d6596cc89..dce2c66562 100644 --- a/src/soc/amd/common/fsp/pci/Kconfig +++ b/src/soc/amd/common/fsp/pci/Kconfig @@ -3,3 +3,10 @@ config SOC_AMD_COMMON_FSP_PCI select SOC_AMD_COMMON_BLOCK_PCI help This option enabled FSP to provide common PCI functions. + +config SOC_AMD_COMMON_FSP_PCIE_CLK_REQ + bool + depends on SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER + help + This option includes code to disable PCIe clock request if the corresponding + PCIe device is disabled. diff --git a/src/soc/amd/common/fsp/pci/Makefile.inc b/src/soc/amd/common/fsp/pci/Makefile.inc index 85418f395f..e0b2cd97a7 100644 --- a/src/soc/amd/common/fsp/pci/Makefile.inc +++ b/src/soc/amd/common/fsp/pci/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_SOC_AMD_COMMON_FSP_PCI),y) -ramstage-y += pci_routing_info.c +ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PCI) += pci_routing_info.c -endif # CONFIG_SOC_AMD_COMMON_FSP_PCI +ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PCIE_CLK_REQ) += pcie_clk_req.c diff --git a/src/soc/amd/common/fsp/pci/pcie_clk_req.c b/src/soc/amd/common/fsp/pci/pcie_clk_req.c new file mode 100644 index 0000000000..881c650ed4 --- /dev/null +++ b/src/soc/amd/common/fsp/pci/pcie_clk_req.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +/* Update gpp glk req config based on DXIO descriptors and enabled devices. */ +void pcie_gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config, + size_t gpp_clk_config_num) +{ + const fsp_dxio_descriptor *dxio_descs = NULL; + const fsp_ddi_descriptor *ddi_descs = NULL; + size_t dxio_num = 0; + size_t ddi_num = 0; + + mainboard_get_dxio_ddi_descriptors(&dxio_descs, &dxio_num, &ddi_descs, &ddi_num); + if (dxio_descs == NULL) { + printk(BIOS_WARNING, + "No DXIO descriptors found, GPP clk req may not reflect enabled devices\n"); + return; + } + + for (int i = 0; i < dxio_num; i++) { + const fsp_dxio_descriptor *dxio_desc = &dxio_descs[i]; + + /* Only consider PCIe and unused engine types. */ + if (dxio_desc->engine_type != PCIE_ENGINE + && dxio_desc->engine_type != UNUSED_ENGINE) + continue; + enum cpm_clk_req dxio_clk_req = dxio_desc->clk_req; + + /* CLK_DISABLE means there's no corresponding clk req line in use */ + if (dxio_clk_req == CLK_DISABLE) + continue; + + /* + * dxio_clk_req is only 4 bits so having CLK_ENABLE as a value for + * a descriptor should cause a compiler error. 0xF isn't a + * valid clk_req value according to AMD's internal code either. + * This is here to draw attention in case this code is ever used + * in a situation where this has changed. + */ + if (dxio_clk_req == (CLK_ENABLE & 0xF)) { + printk(BIOS_WARNING, + "CLK_ENABLE is an invalid clk_req value for PCIe device %d.%d, DXIO descriptor %d\n", + dxio_desc->device_number, dxio_desc->function_number, i); + continue; + } + + /* cpm_clk_req 0 is CLK_DISABLE */ + int gpp_req_index = dxio_clk_req - CLK_REQ0; + /* Ensure that our index is valid */ + if (gpp_req_index < 0 || gpp_req_index >= gpp_clk_config_num) { + printk(BIOS_ERR, + "Failed to convert DXIO clk req value %d to GPP clk req index for PCIe device %d.%d, DXIO descriptor %d, clk req settings may be incorrect\n", + dxio_clk_req, dxio_desc->device_number, + dxio_desc->function_number, i); + continue; + } + + const struct device *pci_device = pcidev_path_on_root( + PCI_DEVFN(dxio_desc->device_number, dxio_desc->function_number)); + if (pci_device == NULL) { + gpp_clk_config[gpp_req_index] = GPP_CLK_OFF; + printk(BIOS_WARNING, + "Cannot find PCIe device %d.%d, disabling GPP clk req %d, DXIO descriptor %d\n", + dxio_desc->device_number, dxio_desc->function_number, i, + gpp_req_index); + continue; + } + + /* PCIe devices haven't been fully set up yet, so directly read the vendor id + * and device id to determine if a device is physically present. If a device + * is not present then the id should be 0xffffffff. 0x00000000, 0xffff0000, + * and 0x0000ffff are there to account for any odd failure cases. */ + u32 id = pci_read_config32(pci_device, PCI_VENDOR_ID); + bool enabled = pci_device->enabled && (id != 0xffffffff) && (id != 0x00000000) + && (id != 0x0000ffff) && (id != 0xffff0000); + + /* Inform of possible mismatches between devices and SoC gpp_clk_config. */ + if (!enabled && gpp_clk_config[gpp_req_index] != GPP_CLK_OFF) { + gpp_clk_config[gpp_req_index] = GPP_CLK_OFF; + printk(BIOS_INFO, + "PCIe device %d.%d disabled, disabling GPP clk req %d, DXIO descriptor %d\n", + dxio_desc->device_number, dxio_desc->function_number, + gpp_req_index, i); + } else if (enabled && gpp_clk_config[gpp_req_index] == GPP_CLK_OFF) { + printk(BIOS_INFO, + "PCIe device %d.%d enabled, GPP clk req is off, DXIO descriptor %d\n", + dxio_desc->device_number, dxio_desc->function_number, i); + } + } +} diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index ef722804b7..d5aae5203b 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -61,7 +61,6 @@ config SOC_AMD_REMBRANDT_BASE select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER - select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 @@ -82,6 +81,7 @@ config SOC_AMD_REMBRANDT_BASE select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI + select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SSE2 select UDK_2017_BINDING diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 9137bc5ce7..d35ecc2a00 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -60,7 +60,6 @@ config SOC_AMD_PHOENIX select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER - select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct @@ -80,6 +79,7 @@ config SOC_AMD_PHOENIX select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SSE2 select UDK_2017_BINDING -- cgit v1.2.3