From 66c6413c69abb7335efc4ea07f4c811c042704b6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 19 Dec 2020 16:19:44 +0200 Subject: ACPI: Refactor ChromeOS specific ACPI GNVS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The layout of GNVS has expectation for a fixed size array for chromeos_acpi_t. This allows us to reduce the exposure of . If chromeos_acpi_t was the last entry in struct global_nvs padding at the end is also removed. If device_nvs_t exists, place a properly sized reserve for chromeos_acpi_t in the middle. Allocation from cbmem is adjusted such that it matches exactly the OperationRegion size defined inside the ASL. Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/amd/picasso/include/soc/nvs.h | 8 -------- src/soc/amd/stoneyridge/include/soc/nvs.h | 8 -------- src/soc/intel/apollolake/include/soc/nvs.h | 8 -------- src/soc/intel/baytrail/include/soc/nvs.h | 6 +----- src/soc/intel/braswell/include/soc/nvs.h | 6 +----- src/soc/intel/broadwell/include/soc/nvs.h | 6 +----- src/soc/intel/common/block/include/intelblocks/nvs.h | 8 -------- src/soc/intel/skylake/include/soc/nvs.h | 8 -------- 8 files changed, 3 insertions(+), 55 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index d5624d4d75..f10fbdde58 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -9,9 +9,7 @@ #ifndef AMD_PICASSO_NVS_H #define AMD_PICASSO_NVS_H -#include #include -#include #include struct __packed global_nvs { @@ -25,12 +23,6 @@ struct __packed global_nvs { uint8_t tmps; /* 0x17 - Temperature Sensor ID */ uint8_t tcrt; /* 0x18 - Critical Threshold */ uint8_t tpsv; /* 0x19 - Passive Threshold */ - uint8_t unused[230]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif /* AMD_PICASSO_NVS_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index 9c479c6e62..e4a158c7cb 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -9,9 +9,7 @@ #ifndef __SOC_STONEYRIDGE_NVS_H__ #define __SOC_STONEYRIDGE_NVS_H__ -#include #include -#include #include struct __packed global_nvs { @@ -32,12 +30,6 @@ struct __packed global_nvs { uint32_t fw01; /* 0x28 - XhciFwRamAddr_Rom, Boot RAM sz/base */ uint32_t fw03; /* 0x2c - XhciFwRomAddr_Ram, Instr RAM sz/base */ uint32_t eh10; /* 0x30 - EHCI BAR */ - uint8_t unused[204]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif /* __SOC_STONEYRIDGE_NVS_H__ */ diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index ab7021cf1a..ae1ae42e1d 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -10,8 +10,6 @@ #define _SOC_APOLLOLAKE_NVS_H_ #include -#include -#include struct __packed global_nvs { /* Miscellaneous */ @@ -35,12 +33,6 @@ struct __packed global_nvs { uint64_t elng; /* 0x35 - 0x3C EPC Length */ uint64_t a4gb; /* 0x3D - 0x44 Base of above 4GB MMIO Resource */ uint64_t a4gs; /* 0x45 - 0x4C Length of above 4GB MMIO Resource */ - uint8_t unused[179]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 6eaf2c804c..1640886d6c 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -4,8 +4,6 @@ #define _BAYTRAIL_NVS_H_ #include -#include -#include #include struct __packed global_nvs { @@ -50,12 +48,10 @@ struct __packed global_nvs { u8 unused[76]; /* ChromeOS specific (0x100-0xfff) */ - chromeos_acpi_t chromeos; + u8 chromeos_reserve[0xf00]; /* Baytrail LPSS (0x1000) */ device_nvs_t dev; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 2184245aa8..2ea114b00c 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -4,9 +4,7 @@ #define _SOC_NVS_H_ #include -#include #include -#include struct __packed global_nvs { /* Miscellaneous */ @@ -52,12 +50,10 @@ struct __packed global_nvs { u8 unused[76]; /* ChromeOS specific (0x100-0xfff) */ - chromeos_acpi_t chromeos; + u8 chromeos_reserve[0xf00]; /* LPSS (0x1000) */ device_nvs_t dev; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 2fe7bc8b70..e0e805253a 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -4,9 +4,7 @@ #define _BROADWELL_NVS_H_ #include -#include #include -#include struct __packed global_nvs { /* Miscellaneous */ @@ -42,12 +40,10 @@ struct __packed global_nvs { u8 unused2[76]; /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; + u8 chromeos_reserve[0xf00]; /* Device specific (0x1000) */ device_nvs_t dev; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 38edfc769c..2f3ac1cc0b 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -4,8 +4,6 @@ #define SOC_INTEL_COMMON_BLOCK_NVS_H #include -#include -#include struct __packed global_nvs { /* Miscellaneous */ @@ -28,12 +26,6 @@ struct __packed global_nvs { u8 uior; /* 0x2f - UART debug controller init on S3 resume */ u64 a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */ u64 a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */ - u8 unused[192]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 303427653c..3d48d4d486 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -4,8 +4,6 @@ #define _SOC_NVS_H_ #include -#include -#include struct __packed global_nvs { /* Miscellaneous */ @@ -48,12 +46,6 @@ struct __packed global_nvs { u64 elng; /* 0x4C - 0x53 EPC Length */ u64 a4gb; /* 0x54 - 0x5B Base of above 4GB MMIO Resource */ u64 a4gs; /* 0x5C - 0x63 Length of above 4GB MMIO Resource */ - u8 rsvd[156]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; }; -check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - #endif -- cgit v1.2.3