From 65783fbeb4d2b8180165b36083023f94bdccbdb7 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 4 Dec 2020 17:38:46 +0100 Subject: soc/amd/cezanne: use common TSC and monotonic timer code Change-Id: I9bc82f1e64f2cf21bfa4bf1ac75d17247208686c Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/48306 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/Kconfig | 3 +-- src/soc/amd/cezanne/Makefile.inc | 1 - src/soc/amd/cezanne/timer.c | 7 ------- 3 files changed, 1 insertion(+), 10 deletions(-) delete mode 100644 src/soc/amd/cezanne/timer.c (limited to 'src/soc') diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 6900ad787a..914384bf9b 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -17,8 +17,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF - select NO_MONOTONIC_TIMER # TODO: replace - select UNKNOWN_TSC_RATE # TODO: replace + select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H config EARLY_RESERVED_DRAM_BASE hex diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index d1d8e97099..d4f585fed8 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -7,7 +7,6 @@ bootblock-y += bootblock.c romstage-y += romstage.c ramstage-y += chip.c -ramstage-y += timer.c CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include diff --git a/src/soc/amd/cezanne/timer.c b/src/soc/amd/cezanne/timer.c deleted file mode 100644 index 9054ffd972..0000000000 --- a/src/soc/amd/cezanne/timer.c +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -void init_timer(void) -{ -} -- cgit v1.2.3