From 6238563b2b65edac8e6dba4f8f20eb020c172317 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 23 Sep 2019 14:38:41 +0200 Subject: soc/intel/skylake: devicetree: introduce PchHdaVcType fsp parameter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make the the FSP Parameter PchHdaVcType a devicetree setting and make use of it in the devicetrees of all boards that currently set it. Signed-off-by: Michael Niewöhner Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35542 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- src/soc/intel/skylake/chip.h | 6 ++++++ src/soc/intel/skylake/chip_fsp20.c | 1 + 2 files changed, 7 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 70fb045baf..944315b47e 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -208,6 +208,12 @@ struct soc_intel_skylake_config { u8 EnableAzalia; u8 DspEnable; + /* HDA Virtual Channel Type Select */ + enum { + Vc0, + Vc1, + } PchHdaVcType; + /* * I/O Buffer Ownership: * 0: HD-A Link diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index e46e52ccd2..462285c2a0 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -361,6 +361,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchIshEnable = dev ? dev->enabled : 0; params->PchHdaEnable = config->EnableAzalia; + params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; params->Device4Enable = config->Device4Enable; -- cgit v1.2.3