From 616f394d3656760deb1e048c0dde4fe3aaa6607f Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 10 Dec 2013 17:12:44 -0800 Subject: baytrail: utilize reg_script_run_on_dev() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The inclusion of reg_script_run_on_dev() allows for removing some of the chained reg_scripts just to set up the device context. Use the new reg_script function in those cases. BUG=None BRANCH=None TEST=Built and booted. Didn't see any bizarre dmesg or coreboot console output. Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/179541 Tested-by: Aaron Durbin Reviewed-by: Duncan Laurie Commit-Queue: Aaron Durbin Reviewed-on: http://review.coreboot.org/5009 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/baytrail/ehci.c | 28 +++++++++++----------------- src/soc/intel/baytrail/emmc.c | 9 ++------- src/soc/intel/baytrail/gfx.c | 15 ++++----------- src/soc/intel/baytrail/lpss.c | 11 ++++------- src/soc/intel/baytrail/pcie.c | 11 ++--------- src/soc/intel/baytrail/scc.c | 3 +-- src/soc/intel/baytrail/xhci.c | 11 ++++------- 7 files changed, 28 insertions(+), 60 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index c6484151ad..d4e29868d6 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -34,7 +34,7 @@ #include "chip.h" -const struct reg_script ehci_init_script[] = { +static const struct reg_script ehci_init_script[] = { /* Enable S0 PLL shutdown * D29:F0:7A[12,10,7,6,4,3,2,1]=11111111b */ REG_PCI_OR16(0x7a, 0x14de), @@ -60,7 +60,7 @@ const struct reg_script ehci_init_script[] = { REG_SCRIPT_END }; -const struct reg_script ehci_clock_gating_script[] = { +static const struct reg_script ehci_clock_gating_script[] = { /* Enable SB local clock gating */ REG_PCI_OR32(0x7c, 0x00004000), /* RCBA + 0x284=0xbe (step B0+) */ @@ -68,7 +68,7 @@ const struct reg_script ehci_clock_gating_script[] = { REG_SCRIPT_END }; -const struct reg_script ehci_disable_script[] = { +static const struct reg_script ehci_disable_script[] = { /* Clear Run/Stop Bit */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0), /* Wait for HC Halted */ @@ -86,6 +86,11 @@ const struct reg_script ehci_disable_script[] = { REG_SCRIPT_END }; +static const struct reg_script ehci_hc_reset[] = { + REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET), + REG_SCRIPT_END +}; + static void usb2_phy_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -121,18 +126,7 @@ static void usb2_phy_init(device_t dev) static void ehci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script ehci_hc_reset[] = { - REG_SCRIPT_SET_DEV(dev), - REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET), - REG_SCRIPT_END - }; - struct reg_script ehci_hc_disable[] = { - REG_SCRIPT_SET_DEV(dev), - REG_SCRIPT_NEXT(ehci_disable_script), - REG_SCRIPT_END - }; struct reg_script ehci_hc_init[] = { - REG_SCRIPT_SET_DEV(dev), /* Controller init */ REG_SCRIPT_NEXT(ehci_init_script), /* Enable clock gating */ @@ -150,19 +144,19 @@ static void ehci_init(device_t dev) /* Don't reset controller in S3 resume path */ if (acpi_slp_type != 3) - reg_script_run(ehci_hc_reset); + reg_script_run_on_dev(dev, ehci_hc_reset); /* Disable controller if ports are routed to XHCI */ if (config->usb_route_to_xhci) { /* Disable controller */ - reg_script_run(ehci_hc_disable); + reg_script_run_on_dev(dev, ehci_disable_script); /* Hide device with southcluster function */ dev->enabled = 0; southcluster_enable_dev(dev); } else { /* Initialize EHCI controller */ - reg_script_run(ehci_hc_init); + reg_script_run_on_dev(dev, ehci_hc_init); } /* Setup USB2 PHY based on board config */ diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index 0a7e9b18dd..a724c4a3f7 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -52,16 +52,11 @@ static const struct reg_script emmc_ops[] = { static void emmc_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), - REG_SCRIPT_NEXT(emmc_ops), - REG_SCRIPT_END, - }; - printk(BIOS_DEBUG, "eMMC init\n"); - reg_script_run(ops); if (config->scc_acpi_mode) scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); + printk(BIOS_DEBUG, "eMMC init\n"); + reg_script_run_on_dev(dev, emmc_ops); } static struct device_operations device_ops = { diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index d2a8ba5d2e..6f78daca36 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -259,14 +259,9 @@ static const struct reg_script gfx_post_vbios_script[] = { REG_SCRIPT_END }; -static void gfx_run_script(device_t dev, const struct reg_script *ops) +static inline void gfx_run_script(device_t dev, const struct reg_script *ops) { - struct reg_script steps[] = { - REG_SCRIPT_SET_DEV(dev), - REG_SCRIPT_NEXT(ops), - REG_SCRIPT_END, - }; - reg_script_run(&steps[0]); + reg_script_run_on_dev(dev, ops); } static void gfx_pre_vbios_init(device_t dev) @@ -294,7 +289,6 @@ static void gfx_panel_setup(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script gfx_pipea_init[] = { - REG_SCRIPT_SET_DEV(dev), /* CONTROL */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), @@ -322,7 +316,6 @@ static void gfx_panel_setup(device_t dev) REG_SCRIPT_END }; struct reg_script gfx_pipeb_init[] = { - REG_SCRIPT_SET_DEV(dev), /* CONTROL */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), @@ -352,12 +345,12 @@ static void gfx_panel_setup(device_t dev) if (config->gpu_pipea_port_select) { printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); - reg_script_run(gfx_pipea_init); + reg_script_run_on_dev(dev, gfx_pipea_init); } if (config->gpu_pipeb_port_select) { printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); - reg_script_run(gfx_pipeb_init); + reg_script_run_on_dev(dev, gfx_pipeb_init); } } diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index e009c7d010..a543fd858c 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -36,7 +36,6 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), @@ -68,20 +67,19 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) gnvs->dev.lpss_en[nvs_index] = 1; /* Put device in ACPI mode */ - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); } static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) { struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), REG_SCRIPT_END, }; - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); } static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) @@ -128,8 +126,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) static void i2c_disable_resets(device_t dev) { /* Release the I2C devices from reset. */ - struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), + static const struct reg_script ops[] = { REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3), REG_SCRIPT_END, }; @@ -146,7 +143,7 @@ static void i2c_disable_resets(device_t dev) CASE_I2C(I2C6): CASE_I2C(I2C7): printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); break; default: return; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index f68304df06..ce76d6d88f 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -90,7 +90,6 @@ static const struct reg_script init_static_after_exit_latency[] = { static void byt_pcie_init(device_t dev) { struct reg_script init_script[] = { - REG_SCRIPT_SET_DEV(dev), REG_SCRIPT_NEXT(init_static_before_exit_latency), /* Exit latency configuration based on * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ @@ -108,7 +107,7 @@ static void byt_pcie_init(device_t dev) REG_SCRIPT_END, }; - reg_script_run(init_script); + reg_script_run_on_dev(dev, init_script); if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -157,19 +156,13 @@ static void check_port_enabled(device_t dev) static void check_device_present(device_t dev) { - struct reg_script no_dev[] = { - REG_SCRIPT_SET_DEV(dev), - REG_SCRIPT_NEXT(no_dev_behind_port), - REG_SCRIPT_END, - }; - /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); /* No device present. */ if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { printk(BIOS_DEBUG, "No PCIe device present.\n"); - reg_script_run(no_dev); + reg_script_run_on_dev(dev, no_dev_behind_port); dev->enabled = 0; } else if(!dev->enabled) { /* Port is disabled, but device present. Disable link. */ diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 64792c2228..7efb66dba1 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -90,7 +90,6 @@ void baytrail_init_scc(void) void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), @@ -122,5 +121,5 @@ void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) gnvs->dev.scc_en[nvs_index] = 1; /* Put device in ACPI mode */ - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); } diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 30e60981e9..e3facb997b 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -132,7 +132,6 @@ const struct reg_script xhci_clock_gating_script[] = { static void xhci_reset_port_usb3(device_t dev, int port) { struct reg_script reset_port_usb3_script[] = { - REG_SCRIPT_SET_DEV(dev), /* Issue Warm Port Rest to the port */ REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), XHCI_USB3_PORTSC_WPR), @@ -145,14 +144,13 @@ static void xhci_reset_port_usb3(device_t dev, int port) ~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST), REG_SCRIPT_END }; - reg_script_run(reset_port_usb3_script); + reg_script_run_on_dev(dev, reset_port_usb3_script); } /* Prepare ports to be routed to EHCI or XHCI */ static void xhci_route_all(device_t dev) { - struct reg_script xhci_route_all_script[] = { - REG_SCRIPT_SET_DEV(dev), + static const struct reg_script xhci_route_all_script[] = { /* USB3 SuperSpeed Enable */ REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP), /* USB2 Port Route to XHCI */ @@ -165,7 +163,7 @@ static void xhci_route_all(device_t dev) printk(BIOS_INFO, "USB: Route ports to XHCI controller\n"); /* Route ports to XHCI controller */ - reg_script_run(xhci_route_all_script); + reg_script_run_on_dev(dev, xhci_route_all_script); /* Reset enabled USB3 ports */ port_disabled = pci_read_config32(dev, XHCI_USB3PDO); @@ -180,7 +178,6 @@ static void xhci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { - REG_SCRIPT_SET_DEV(dev), /* Setup USB3 phy */ REG_SCRIPT_NEXT(usb3_phy_script), /* Initialize host controller */ @@ -207,7 +204,7 @@ static void xhci_init(device_t dev) }; /* Initialize XHCI controller */ - reg_script_run(xhci_hc_init); + reg_script_run_on_dev(dev, xhci_hc_init); /* Route all ports to XHCI if requested */ if (config->usb_route_to_xhci) -- cgit v1.2.3