From 5cabc29013759f667a9a08a88c58468485749ac9 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 21 Apr 2023 16:17:21 +0200 Subject: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers Signed-off-by: Felix Held Change-Id: I95916e409b3fbd4941a861054733a34100244da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74657 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Karthik Ramasubramanian Reviewed-by: Fred Reitberger --- src/soc/amd/phoenix/xhci.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/phoenix/xhci.c b/src/soc/amd/phoenix/xhci.c index 8bb446f9f9..99033f94c6 100644 --- a/src/soc/amd/phoenix/xhci.c +++ b/src/soc/amd/phoenix/xhci.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Phoenix */ - #include #include #include @@ -24,6 +22,18 @@ static const struct sci_source xhci_sci_sources[] = { .gpe = XHCI_GEVENT, .direction = SMI_SCI_LVL_HIGH, .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC3_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC4_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG } }; @@ -45,6 +55,16 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) } } + if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { + if (dev->path.pci.devfn == USB4_XHCI0_DEVFN) { + *gpe = xhci_sci_sources[2].gpe; + return CB_SUCCESS; + } else if (dev->path.pci.devfn == USB4_XHCI1_DEVFN) { + *gpe = xhci_sci_sources[3].gpe; + return CB_SUCCESS; + } + } + return CB_ERR_ARG; } -- cgit v1.2.3