From 5c8d43e207b4349e95ffb359e0ed08ffa3f789a0 Mon Sep 17 00:00:00 2001 From: Kevin L Lee Date: Fri, 12 Dec 2014 14:02:43 +0800 Subject: baytrail: fix the coding error on PCIe L1 exit latency The original code uses L1EXIT_MASK to shift the bit for PCIe L1 exit latency, the code should use L1EXIT_SHIFT for bit shifting. BUG=chrome-os-partner:34037 BRANCH=None TEST=build and boot on candy, verify B0:D28:F0 + 4Ch [17:15] set to 010b. Correspond WIFI device performance got improvement. Signed-off-by: Kevin L Lee Change-Id: I3ac5b6319b726aa16cdb9678face89022d979517 Signed-off-by: Stefan Reinauer Original-Commit-Id: 381827e3d92c9e786cd8ebe412586968662fb4be Original-Change-Id: I8171f80720830cfa76f26778ae31c7590a723b92 Original-Reviewed-on: https://chromium-review.googlesource.com/234673 Original-Reviewed-by: Kenji Chen Original-Reviewed-by: Shawn Nematbakhsh Original-Tested-by: Kenji Chen Original-Commit-Queue: Kenji Chen Reviewed-on: http://review.coreboot.org/9480 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc') diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 187015801d..e44ebc66dd 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -95,7 +95,7 @@ static void byt_pcie_init(device_t dev) /* Exit latency configuration based on * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ REG_PCI_RMW32(LCAP, ~L1EXIT_MASK, - 2 << (L1EXIT_MASK + pll_en_off)), + 2 << (L1EXIT_SHIFT + pll_en_off)), REG_SCRIPT_NEXT(init_static_after_exit_latency), /* Disable hot plug, set power to 10W, set slot number. */ REG_PCI_RMW32(SLCAP, ~(HPC | HPS), -- cgit v1.2.3