From 5468e94df1f1f017a936a2a619e57741ecfbd132 Mon Sep 17 00:00:00 2001 From: Jenny TC Date: Thu, 18 Jun 2015 14:02:00 +0530 Subject: intel/braswell: fix build Commit "BCRD2: Enable LPDDR3" with the Change-Id listed below contained additions to braswell's chip.h which were lost during merging. BRANCH=None BUG=None TEST=google/strago builds Change-Id: I995b788b6a308cefa23228544127bb1e384bbcc7 Signed-off-by: Patrick Georgi Original-Commit-Id: 561edf23ab696772fd0a6af34cb435db9d96e912 Original-Change-Id: Ie08900bc62d517394412cc597274fb8f5b6b0f51 Original-Signed-off-by: Patrick Georgi Original-Original-Change-Id: I1cb5a03b77baf2df125b648dd75c9f8166f5571e Original-Original-Signed-off-by: Jenny TC Original-Original-Signed-off-by: Divagar Mohandass Original-Original-Reviewed-on: https://chromium-review.googlesource.com/282155 Original-Reviewed-on: https://chromium-review.googlesource.com/288880 Original-Reviewed-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/11065 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/braswell/chip.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 7422bc4c09..191fc01926 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -34,6 +34,9 @@ #define SVID_CONFIG3 3 #define SVID_PMIC_CONFIG 8 +#define MEM_DDR3 0 +#define MEM_LPDDR3 1 + struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable; -- cgit v1.2.3