From 4feef09c658210c1d28e4dedbbb95374b8b13527 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 13 Nov 2020 23:58:41 +0100 Subject: soc/amd/picasso/include: unify include guards Change-Id: I980cdd03d4283cd4bd9db8bd90fde9a43bebc1e5 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47580 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/picasso/include/soc/acp.h | 6 +++--- src/soc/amd/picasso/include/soc/acpi.h | 6 +++--- src/soc/amd/picasso/include/soc/amd_pci_int_defs.h | 6 +++--- src/soc/amd/picasso/include/soc/cpu.h | 6 +++--- src/soc/amd/picasso/include/soc/data_fabric.h | 6 +++--- src/soc/amd/picasso/include/soc/gpio.h | 6 +++--- src/soc/amd/picasso/include/soc/i2c.h | 6 +++--- src/soc/amd/picasso/include/soc/iomap.h | 6 +++--- src/soc/amd/picasso/include/soc/memmap.h | 6 +++--- src/soc/amd/picasso/include/soc/mrc_cache.h | 6 +++--- src/soc/amd/picasso/include/soc/msr.h | 6 +++--- src/soc/amd/picasso/include/soc/nvs.h | 6 +++--- src/soc/amd/picasso/include/soc/pci_devs.h | 6 +++--- src/soc/amd/picasso/include/soc/platform_descriptors.h | 6 +++--- src/soc/amd/picasso/include/soc/psp_transfer.h | 6 +++--- src/soc/amd/picasso/include/soc/reset.h | 6 +++--- src/soc/amd/picasso/include/soc/smi.h | 6 +++--- src/soc/amd/picasso/include/soc/smu.h | 6 +++--- src/soc/amd/picasso/include/soc/soc_util.h | 6 +++--- src/soc/amd/picasso/include/soc/southbridge.h | 6 +++--- src/soc/amd/picasso/include/soc/uart.h | 6 +++--- 21 files changed, 63 insertions(+), 63 deletions(-) (limited to 'src/soc') diff --git a/src/soc/amd/picasso/include/soc/acp.h b/src/soc/amd/picasso/include/soc/acp.h index 545a372100..f812b32a98 100644 --- a/src/soc/amd/picasso/include/soc/acp.h +++ b/src/soc/amd/picasso/include/soc/acp.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PI_PICASSO_ACP_H__ -#define __PI_PICASSO_ACP_H__ +#ifndef AMD_PICASSO_ACP_H +#define AMD_PICASSO_ACP_H /* Bus A D0F5 - Audio Processor */ #define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ @@ -11,4 +11,4 @@ #define ACP_PME_EN 0x1418 #define PME_EN_MASK (1 << 0) -#endif /* __PI_PICASSO_ACP_H__ */ +#endif /* AMD_PICASSO_ACP_H */ diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index a21d3477bb..bc444f85ae 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __SOC_PICASSO_ACPI_H__ -#define __SOC_PICASSO_ACPI_H__ +#ifndef AMD_PICASSO_ACPI_H +#define AMD_PICASSO_ACPI_H #include #include @@ -21,4 +21,4 @@ struct chipset_state { struct gpio_wake_state gpio_state; }; -#endif /* __SOC_PICASSO_ACPI_H__ */ +#endif /* AMD_PICASSO_ACPI_H */ diff --git a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h index 3082287031..7f75de98c5 100644 --- a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_PCI_INT_DEFS_H__ -#define __AMD_PCI_INT_DEFS_H__ +#ifndef AMD_PICASSO_AMD_PCI_INT_DEFS_H +#define AMD_PICASSO_AMD_PCI_INT_DEFS_H /* * PIRQ and device routing - these define the index into the @@ -61,4 +61,4 @@ #define PIRQ_UART3 0x79 /* UART3 */ /* 0x7a-0x7f reserved */ -#endif /* __AMD_PCI_INT_DEFS_H__ */ +#endif /* AMD_PICASSO_AMD_PCI_INT_DEFS_H */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index cbc3929a78..3f6cd247c2 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_CPU_H__ -#define __PICASSO_CPU_H__ +#ifndef AMD_PICASSO_CPU_H +#define AMD_PICASSO_CPU_H int get_cpu_count(void); void check_mca(void); @@ -19,4 +19,4 @@ void check_mca(void); #define RAVEN2_VBIOS_VID_DID 0x100215dd /* VID/DID in RV2 VBIOS header */ #define RAVEN2_VBIOS_REV 0xc4 -#endif /* __PICASSO_CPU_H__ */ +#endif /* AMD_PICASSO_CPU_H */ diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 39906e8f95..842cb946a7 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_PICASSO_DATAFABRIC_H__ -#define __SOC_PICASSO_DATAFABRIC_H__ +#ifndef AMD_PICASSO_DATA_FABRIC_H +#define AMD_PICASSO_DATA_FABRIC_H #include @@ -26,4 +26,4 @@ void data_fabric_set_mmio_np(void); -#endif /* __SOC_PICASSO_DATAFABRIC_H__ */ +#endif /* AMD_PICASSO_DATA_FABRIC_H */ diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index 370b29f1e0..4fbb937461 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_GPIO_H__ -#define __PICASSO_GPIO_H__ +#ifndef AMD_PICASSO_GPIO_H +#define AMD_PICASSO_GPIO_H #define GPIO_DEVICE_NAME "AMD0030" #define GPIO_DEVICE_DESC "GPIO Controller" @@ -297,4 +297,4 @@ #define GPIO_2_EVENT GEVENT_8 #endif /* __ACPI__ */ -#endif /* __PICASSO_GPIO_H__ */ +#endif /* AMD_PICASSO_GPIO_H */ diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index c1dd6ef6ff..3e94a1ad62 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_I2C_H__ -#define __PICASSO_I2C_H__ +#ifndef AMD_PICASSO_I2C_H +#define AMD_PICASSO_I2C_H #include #include @@ -26,4 +26,4 @@ void sb_reset_i2c_slaves(void); /* Sets the base address for the specific I2C bus. */ void i2c_set_bar(unsigned int bus, uintptr_t bar); -#endif /* __PICASSO_I2C_H__ */ +#endif /* AMD_PICASSO_I2C_H */ diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 890b1c3647..a49768f129 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_PICASSO_IOMAP_H__ -#define __SOC_PICASSO_IOMAP_H__ +#ifndef AMD_PICASSO_IOMAP_H +#define AMD_PICASSO_IOMAP_H /* MMIO Ranges */ /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ @@ -90,4 +90,4 @@ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ -#endif /* __SOC_PICASSO_IOMAP_H__ */ +#endif /* AMD_PICASSO_IOMAP_H */ diff --git a/src/soc/amd/picasso/include/soc/memmap.h b/src/soc/amd/picasso/include/soc/memmap.h index c27b165142..53c9d310b0 100644 --- a/src/soc/amd/picasso/include/soc/memmap.h +++ b/src/soc/amd/picasso/include/soc/memmap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __SOC_AMD_PICASSO_MEMMAP_H__ -#define __SOC_AMD_PICASSO_MEMMAP_H__ +#ifndef AMD_PICASSO_MEMMAP_H +#define AMD_PICASSO_MEMMAP_H #include #include @@ -16,4 +16,4 @@ struct memmap_early_dram { void memmap_stash_early_dram_usage(void); const struct memmap_early_dram *memmap_get_early_dram_usage(void); -#endif /* __SOC_AMD_PICASSO_MEMMAP_H__ */ +#endif /* AMD_PICASSO_MEMMAP_H */ diff --git a/src/soc/amd/picasso/include/soc/mrc_cache.h b/src/soc/amd/picasso/include/soc/mrc_cache.h index ed63ba86fb..c7fcedbdd9 100644 --- a/src/soc/amd/picasso/include/soc/mrc_cache.h +++ b/src/soc/amd/picasso/include/soc/mrc_cache.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __PICASSO_MRC_CACHE_H__ -#define __PICASSO_MRC_CACHE_H__ +#ifndef AMD_PICASSO_MRC_CACHE_H +#define AMD_PICASSO_MRC_CACHE_H void *soc_fill_mrc_cache(void); void soc_update_mrc_cache(void); -#endif /* __PICASSO_MRC_CACHE_H__ */ +#endif /* AMD_PICASSO_MRC_CACHE_H */ diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h index 0743ba0c9e..841e6a5a0d 100644 --- a/src/soc/amd/picasso/include/soc/msr.h +++ b/src/soc/amd/picasso/include/soc/msr.h @@ -4,8 +4,8 @@ * The definitions come from the device's PPR. */ -#ifndef SOC_AMD_PICASSO_MSR_H -#define SOC_AMD_PICASSO_MSR_H +#ifndef AMD_PICASSO_MSR_H +#define AMD_PICASSO_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ #define PSTATE_DEF_HI_ENABLE_SHIFT 31 @@ -25,4 +25,4 @@ #define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) #define PSTATE_DEF_LO_CORE_FREQ_BASE 25 -#endif /* SOC_AMD_PICASSO_MSR_H */ +#endif /* AMD_PICASSO_MSR_H */ diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 2abcdd31f7..d5624d4d75 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -6,8 +6,8 @@ * */ -#ifndef __SOC_PICASSO_NVS_H__ -#define __SOC_PICASSO_NVS_H__ +#ifndef AMD_PICASSO_NVS_H +#define AMD_PICASSO_NVS_H #include #include @@ -33,4 +33,4 @@ struct __packed global_nvs { check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -#endif /* __SOC_PICASSO_NVS_H__ */ +#endif /* AMD_PICASSO_NVS_H */ diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 83c0bcc7e3..3f18bd5414 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PI_PICASSO_PCI_DEVS_H__ -#define __PI_PICASSO_PCI_DEVS_H__ +#ifndef AMD_PICASSO_PCI_DEVS_H +#define AMD_PICASSO_PCI_DEVS_H #include #include @@ -118,4 +118,4 @@ #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) -#endif /* __PI_PICASSO_PCI_DEVS_H__ */ +#endif /* AMD_PICASSO_PCI_DEVS_H */ diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h index 0ea6f2b338..fc7f14071d 100644 --- a/src/soc/amd/picasso/include/soc/platform_descriptors.h +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_PLATFORM_DESCRIPTORS_H__ -#define __PICASSO_PLATFORM_DESCRIPTORS_H__ +#ifndef AMD_PICASSO_PLATFORM_DESCRIPTORS_H +#define AMD_PICASSO_PLATFORM_DESCRIPTORS_H #include #include @@ -27,4 +27,4 @@ void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num); -#endif /* __PICASSO_PLATFORM_DESCRIPTORS_H__ */ +#endif /* AMD_PICASSO_PLATFORM_DESCRIPTORS_H */ diff --git a/src/soc/amd/picasso/include/soc/psp_transfer.h b/src/soc/amd/picasso/include/soc/psp_transfer.h index afc4d7d1ac..ce197c11e2 100644 --- a/src/soc/amd/picasso/include/soc/psp_transfer.h +++ b/src/soc/amd/picasso/include/soc/psp_transfer.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef PSP_VERSTAGE_PSP_TRANSFER_H -#define PSP_VERSTAGE_PSP_TRANSFER_H +#ifndef AMD_PICASSO_PSP_TRANSFER_H +#define AMD_PICASSO_PSP_TRANSFER_H # if (CONFIG_CMOS_RECOVERY_BYTE != 0) # define CMOS_RECOVERY_BYTE CONFIG_CMOS_RECOVERY_BYTE @@ -49,4 +49,4 @@ void show_psp_transfer_info(void); #endif -#endif /* PSP_VERSTAGE_PSP_TRANSFER_H */ +#endif /* AMD_PICASSO_PSP_TRANSFER_H */ diff --git a/src/soc/amd/picasso/include/soc/reset.h b/src/soc/amd/picasso/include/soc/reset.h index bb2ee84e03..fb47068ea0 100644 --- a/src/soc/amd/picasso/include/soc/reset.h +++ b/src/soc/amd/picasso/include/soc/reset.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PI_PICASSO_RESET_H__ -#define __PI_PICASSO_RESET_H__ +#ifndef AMD_PICASSO_RESET_H +#define AMD_PICASSO_RESET_H void set_warm_reset_flag(void); int is_warm_reset(void); -#endif /* __PI_PICASSO_RESET_H__ */ +#endif /* AMD_PICASSO_RESET_H */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 6413c6a06d..1f08efe3ac 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ -#define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ +#ifndef AMD_PICASSO_SMI_H +#define AMD_PICASSO_SMI_H #include @@ -221,4 +221,4 @@ void disable_gevent_smi(uint8_t gevent); void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event); -#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */ +#endif /* AMD_PICASSO_SMI_H */ diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h index c402508653..2dd0e7b6a2 100644 --- a/src/soc/amd/picasso/include/soc/smu.h +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_SMU_H__ -#define __PICASSO_SMU_H__ +#ifndef AMD_PICASSO_SMU_H +#define AMD_PICASSO_SMU_H /* * SMU mailbox register offsets in indirect address space accessed by an index/data pair in @@ -23,4 +23,4 @@ enum smu_message_id { */ void smu_sx_entry(void); -#endif /* __PICASSO_SMU_H__ */ +#endif /* AMD_PICASSO_SMU_H */ diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h index 0de0643249..e03a78e8da 100644 --- a/src/soc/amd/picasso/include/soc/soc_util.h +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_SOC_UTIL_H__ -#define __PICASSO_SOC_UTIL_H__ +#ifndef AMD_PICASSO_SOC_UTIL_H +#define AMD_PICASSO_SOC_UTIL_H #include @@ -39,4 +39,4 @@ bool soc_is_reduced_io_sku(void); /* function to determine the iGPU type */ bool soc_is_raven2(void); -#endif /* __PICASSO_SOC_UTIL_H__ */ +#endif /* AMD_PICASSO_SOC_UTIL_H */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 222858ab51..d193661985 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_SB_H__ -#define __PICASSO_SB_H__ +#ifndef AMD_PICASSO_SOUTHBRIDGE_H +#define AMD_PICASSO_SOUTHBRIDGE_H #include #include @@ -294,4 +294,4 @@ void i2c_soc_init(void); /* Allow the board to change the default I2C pad configuration */ void mainboard_i2c_override(int bus, uint32_t *pad_settings); -#endif /* __PICASSO_SB_H__ */ +#endif /* AMD_PICASSO_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/picasso/include/soc/uart.h b/src/soc/amd/picasso/include/soc/uart.h index 4e5619fa86..051c8bf4d5 100644 --- a/src/soc/amd/picasso/include/soc/uart.h +++ b/src/soc/amd/picasso/include/soc/uart.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_UART_H__ -#define __PICASSO_UART_H__ +#ifndef AMD_PICASSO_UART_H +#define AMD_PICASSO_UART_H #include @@ -10,4 +10,4 @@ void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART * uintptr_t get_uart_base(unsigned int idx); /* get MMIO base address of FCH UART */ -#endif /* __PICASSO_UART_H__ */ +#endif /* AMD_PICASSO_UART_H */ -- cgit v1.2.3