From 4f1147b54124609284e390b9a1176a90877848f5 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Tue, 9 Feb 2021 10:56:47 -0700 Subject: soc/amd/picasso: Add SPI registers The picasso SPI registers are different than the ones defined in amdblocks/lpc.h. The BASE_ALIGNMENT has changed and the PSP_SPI_MMIO_SEL bit has been added. Signed-off-by: Raul E Rangel Change-Id: I0b5a0c88c6dbb95cdbc62b949a7d30bfad1fa725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50444 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/include/soc/lpc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 src/soc/amd/picasso/include/soc/lpc.h (limited to 'src/soc') diff --git a/src/soc/amd/picasso/include/soc/lpc.h b/src/soc/amd/picasso/include/soc/lpc.h new file mode 100644 index 0000000000..2705f2d9e5 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/lpc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_PICASSO_LPC_H +#define AMD_PICASSO_LPC_H + +#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ALIGNMENT BIT(8) +#define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) +#define PSP_SPI_MMIO_SEL BIT(4) +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ABORT_ENABLE BIT(2) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_ROM_ALT_ENABLE BIT(0) +#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4)) + +#endif /* AMD_PICASSO_LPC_H */ -- cgit v1.2.3