From 4ee03dc445cf4f4b625d85141c442e03e6a64d00 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Mon, 24 Apr 2023 17:13:58 -0700
Subject: soc/intel/alderlake: Reduce memory test size

Enable upd to reduce size of the memory test.

BUG=b:268546941
TEST=Observe boot time improvement with these two UPDs set

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I95c7d8503596c2712d7abe123ed1f911ac4abacf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
---
 src/soc/intel/alderlake/chipset.cb | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/soc')

diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index ed8ae049fa..e41cd842c8 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -90,6 +90,9 @@ chip soc/intel/alderlake
 		.tdp_pl4 = 114,
 	}"
 
+	# Reduce the size of BasicMemoryTests to speed up the boot time.
+	register "lower_basic_mem_test_size" = "true"
+
 	# NOTE: if any variant wants to override this value, use the same format
 	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
 	# putting it under register "common_soc_config" in overridetree.cb file.
-- 
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