From 4e6b7907de07c9c7d4b01a6213a8e13e946398cb Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 2 Oct 2018 08:44:47 +0200 Subject: src: Fix MSR_PKG_CST_CONFIG_CONTROL register name Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/28871 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/soc/intel/apollolake/cpu.c | 2 +- src/soc/intel/baytrail/cpu.c | 2 +- src/soc/intel/baytrail/include/soc/msr.h | 2 +- src/soc/intel/braswell/cpu.c | 2 +- src/soc/intel/braswell/include/soc/msr.h | 2 +- src/soc/intel/broadwell/cpu.c | 4 ++-- src/soc/intel/broadwell/include/soc/msr.h | 2 +- src/soc/intel/common/block/include/intelblocks/msr.h | 10 +++++----- src/soc/intel/denverton_ns/include/soc/msr.h | 2 +- src/soc/intel/fsp_baytrail/cpu.c | 2 +- src/soc/intel/fsp_baytrail/include/soc/msr.h | 2 +- 11 files changed, 16 insertions(+), 16 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index caa3bbf90f..e74599694d 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -47,7 +47,7 @@ static const struct reg_script core_msr_script[] = { #if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) /* Enable C-state and IO/MWAIT redirect */ - REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL, + REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL, (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK | IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)), /* Power Management I/O base address for I/O trapping to C-states */ diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 618430b9a8..9bbeafbe76 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -35,7 +35,7 @@ /* Core level MSRs */ const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), + REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), /* Disable C1E */ diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index 689d4d55cc..b332478734 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -19,7 +19,7 @@ #define MSR_IA32_PLATFORM_ID 0x17 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 85b04ac81f..6ed12afa5f 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -36,7 +36,7 @@ /* Core level MSRs */ static const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), + REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), /* Disable C1E */ diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 47e9bcd430..1a79b2faf5 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -21,7 +21,7 @@ #define MSR_IA32_BIOS_SIGN_ID 0x8B #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index ee1fd528cc..3ef0d722b6 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -394,7 +394,7 @@ static void configure_c_states(void) { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 31); // Timed MWAIT Enable msr.lo |= (1 << 30); // Package c-state Undemotion Enable msr.lo |= (1 << 29); // Package c-state Demotion Enable @@ -404,7 +404,7 @@ static void configure_c_states(void) msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection /* The deepest package c-state defaults to factory-configured value. */ - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 41ce17c10b..c2a939e392 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -23,7 +23,7 @@ #define CPUID_SMX (1 << 6) #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c #define SMM_MCA_CAP_MSR 0x17d diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index e1fc431f3a..154f03b81e 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -25,14 +25,14 @@ #define SGX_GLOBAL_ENABLE (1 << 18) #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PLATFORM_INFO 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 +/* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ #define PKG_C_STATE_LIMIT_C2_MASK 0x2 -/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ +/* Set MSR_PKG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ #define CORE_C_STATE_LIMIT_C10_MASK 0x70 -/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ +/* Set MSR_PKG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ #define IO_MWAIT_REDIRECT_MASK 0x400 -/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ +/* Set MSR_PKG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ #define CST_CFG_LOCK_MASK 0x8000 #define MSR_BIOS_UPGD_TRIG 0x7a #define SGX_ACTIVATE_BIT (1) diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 4d1ac70c3a..a2a42f178e 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -26,7 +26,7 @@ #define CPUID_SMX (1 << 6) #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c #define SMM_MCA_CAP_MSR 0x17d diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index a69d046e7b..89ea4c2ada 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -35,7 +35,7 @@ /* Core level MSRs */ static const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), + REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), REG_MSR_OR(MSR_POWER_MISC, 0x44), diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h index ea1d790867..4435256be8 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h @@ -19,7 +19,7 @@ #define MSR_IA32_PLATFORM_ID 0x17 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_POWER_MISC 0x120 #define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 -- cgit v1.2.3