From 4c18de2de918e96ceeca87d2fb51853c286548ee Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Sat, 30 Jul 2016 07:17:13 -0700 Subject: soc/intel/common: Enable MTRR display during bootblock & postcar MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update Makefile.inc to allow MTRR display during bootblock and postcar. TEST=Build and run on Galileo Gen2 Change-Id: If12896df46b9edfc9fff3fab3a12d2dae23517a3 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/15990 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/common/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 429c61c2e1..13ba21bcbe 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,5 +1,7 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) +bootblock-y += util.c + verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c @@ -12,6 +14,8 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c +postcar-y += util.c + ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c -- cgit v1.2.3