From 4bd9187dadaf4f3be5a1776d98d1f79cdfb23de8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Tue, 16 Mar 2021 19:02:26 +0200
Subject: ACPI: Refactor use of global and device NVS
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After ChromeOS NVS was moved to a separate allocation and the use
of multiple OperationRegions, maintaining the fixed offsets is not
necessary.

Use actual structure size for OperationRegions, but align the
allocations to 8 bytes or sizeof(uint64_t).

Change-Id: I9c73b7c44d234af42c571b23187b924ca2c3894a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/baytrail/Kconfig      | 1 -
 src/soc/intel/baytrail/ramstage.c   | 6 ++++++
 src/soc/intel/baytrail/smihandler.c | 4 +---
 src/soc/intel/braswell/Kconfig      | 1 -
 src/soc/intel/braswell/acpi.c       | 6 ++++++
 5 files changed, 13 insertions(+), 5 deletions(-)

(limited to 'src/soc')

diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index a9ba092279..9af65ee062 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -8,7 +8,6 @@ if SOC_INTEL_BAYTRAIL
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
-	select ACPI_HAS_DEVICE_NVS
 	select ARCH_ALL_STAGES_X86_32
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select BOOT_DEVICE_SUPPORTS_WRITES
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 0b681b0212..26e0b6e46d 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -13,6 +13,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 
+#include <soc/device_nvs.h>
 #include <soc/gpio.h>
 #include <soc/lpc.h>
 #include <soc/msr.h>
@@ -116,6 +117,11 @@ static void fill_in_pattrs(void)
 	attrs->bclk_khz = bus_freq_khz();
 }
 
+size_t size_of_dnvs(void)
+{
+	return sizeof(struct device_nvs);
+}
+
 /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
 static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps)
 {
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index e48ddbacab..20e15902b1 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -20,8 +20,6 @@
 #include <soc/nvs.h>
 #include <soc/device_nvs.h>
 
-#include <vendorcode/google/chromeos/gnvs.h>
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {
@@ -210,7 +208,7 @@ static void southbridge_smi_gsmi(void)
 
 void *acpi_get_device_nvs(void)
 {
-	return (u8 *)gnvs + GNVS_DEVICE_NVS_OFFSET;
+	return (u8 *)gnvs + ALIGN_UP(sizeof(struct global_nvs), sizeof(uint64_t));
 }
 
 /*
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index f91e7de18c..9a55672e36 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -8,7 +8,6 @@ if SOC_INTEL_BRASWELL
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
-	select ACPI_HAS_DEVICE_NVS
 	select ARCH_ALL_STAGES_X86_32
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select BOOT_DEVICE_SUPPORTS_WRITES
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 2d7ca3c9ca..c70b69dc21 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -13,6 +13,7 @@
 #include <device/pci.h>
 #include <drivers/intel/gma/opregion.h>
 #include <soc/acpi.h>
+#include <soc/device_nvs.h>
 #include <soc/gfx.h>
 #include <soc/iomap.h>
 #include <soc/irq.h>
@@ -60,6 +61,11 @@ static acpi_cstate_t cstate_map[] = {
 	}
 };
 
+size_t size_of_dnvs(void)
+{
+	return sizeof(struct device_nvs);
+}
+
 void soc_fill_gnvs(struct global_nvs *gnvs)
 {
 	/* Fill in the Wi-Fi Region ID */
-- 
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