From 4a04a7bf10d7b2c372247fce297f7a69b85de250 Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Fri, 8 Jan 2016 16:02:13 +0800 Subject: mediatek/mt8173: Add display driver BRANCH=none BUG=none TEST=saw bootloader screen on rev4 and rev5 with CL:331813 Change-Id: Ibb01cf251276d2c059739f10e166fefd0de35460 Signed-off-by: Patrick Georgi Original-Commit-Id: 8d52a4c486b75b99dc25657ccb6ed90f671c26d6 Original-Change-Id: I4efe439d52b5a5516145960bcffb340152bfba53 Original-Signed-off-by: Jitao Shi Original-Reviewed-on: https://chromium-review.googlesource.com/331812 Original-Commit-Ready: Yidi Lin Original-Tested-by: Yidi Lin Original-Reviewed-by: Julius Werner Original-Reviewed-by: Daniel Kurtz Reviewed-on: https://review.coreboot.org/14689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/mediatek/mt8173/Makefile.inc | 3 + src/soc/mediatek/mt8173/ddp.c | 179 ++++++++++ src/soc/mediatek/mt8173/dsi.c | 300 ++++++++++++++++ src/soc/mediatek/mt8173/include/soc/addressmap.h | 15 + src/soc/mediatek/mt8173/include/soc/ddp.h | 432 +++++++++++++++++++++++ src/soc/mediatek/mt8173/include/soc/dsi.h | 269 ++++++++++++++ 6 files changed, 1198 insertions(+) create mode 100644 src/soc/mediatek/mt8173/ddp.c create mode 100644 src/soc/mediatek/mt8173/dsi.c create mode 100644 src/soc/mediatek/mt8173/include/soc/ddp.h create mode 100644 src/soc/mediatek/mt8173/include/soc/dsi.h (limited to 'src/soc') diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 82d74e31f6..b79492d19c 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -75,6 +75,9 @@ ramstage-y += rtc.c ramstage-y += usb.c +ramstage-y += ddp.c +ramstage-y += dsi.c + ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c BL31_MAKEARGS += PLAT=mt8173 diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c new file mode 100644 index 0000000000..b7a8a6b670 --- /dev/null +++ b/src/soc/mediatek/mt8173/ddp.c @@ -0,0 +1,179 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) +#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) + +static void disp_config_main_path_connection(void) +{ + write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_COLOR0); + + write32(&mmsys_cfg->disp_od_mout_en, OD_MOUT_EN_RDMA0); + + write32(&mmsys_cfg->disp_ufoe_mout_en, UFOE_MOUT_EN_DSI0); + + write32(&mmsys_cfg->disp_color0_sel_in, COLOR0_SEL_IN_OVL0); +} + +static void disp_config_main_path_mutex(void) +{ + write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + + /* Clock source from DSI0 */ + write32(&disp_mutex->mutex[0].sof, BIT(0)); + write32(&disp_mutex->mutex[0].en, BIT(0)); +} + +static void ovl_set_roi(u32 width, u32 height, u32 color) +{ + write32(&disp_ovl[0]->roi_size, height << 16 | width); + write32(&disp_ovl[0]->roi_bgclr, color); +} + +static void ovl_layer_enable(void) +{ + write32(&disp_ovl[0]->rdma[0].ctrl, BIT(0)); + write32(&disp_ovl[0]->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); + + setbits_le32(&disp_ovl[0]->src_con, BIT(0)); +} + +static void rdma_start(void) +{ + setbits_le32(&disp_rdma[0]->global_con, RDMA_ENGINE_EN); +} + +static void rdma_config(u32 width, u32 height, u32 pixel_clk) +{ + u32 threshold; + u32 reg; + + /* Config width */ + clrsetbits_le32(&disp_rdma[0]->size_con_0, 0x1FFF, width); + + /* Config height */ + clrsetbits_le32(&disp_rdma[0]->size_con_1, 0xFFFFF, height); + + /* + * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the + * FIFO pseudo size reset default of 8 KiB. Set the output threshold to + * 6 microseconds with 7/6 overhead to account for blanking, and with a + * pixel depth of 4 bytes: + */ + + threshold = pixel_clk * 4 * 7 / 1000; + + reg = RDMA_FIFO_UNDERFLOW_EN | + RDMA_FIFO_PSEUDO_SIZE(8 * KiB) | + RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); + + write32(&disp_rdma[0]->fifo_con, reg); +} + +static void od_start(u32 width, u32 height) +{ + write32(&disp_od->size, width << 16 | height); + write32(&disp_od->cfg, OD_RELAY_MODE); + + write32(&disp_od->en, 1); +} + +static void ufoe_start(void) +{ + write32(&disp_ufoe->start, UFO_BYPASS); +} + +static void color_start(u32 width, u32 height) +{ + write32(&disp_color[0]->width, width); + write32(&disp_color[0]->height, height); + write32(&disp_color[0]->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL); + write32(&disp_color[0]->start, BIT(0)); +} + +static void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height) +{ + write32(&disp_ovl[0]->layer[0].con, fmt << 12); + write32(&disp_ovl[0]->layer[0].src_size, height << 16 | width); + write32(&disp_ovl[0]->layer[0].pitch, (width * bpp) & 0xFFFF); + + ovl_layer_enable(); +} + +static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk) +{ + /* Setup OVL */ + ovl_set_roi(width, height, 0); + + /* Setup RDMA0 */ + rdma_config(width, height, pixel_clk); + + /* Setup OD */ + od_start(width, height); + + /* Setup UFOE */ + ufoe_start(); + + /* Setup Color */ + color_start(width, height); + + /* Setup main path connection */ + disp_config_main_path_connection(); + + /* Setup main path mutex */ + disp_config_main_path_mutex(); +} + +static void disp_clock_on(void) +{ + clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_SMI_COMMON | + CG_CON0_SMI_LARB0 | + CG_CON0_MUTEX_32K | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_COLOR0 | + CG_CON0_DISP_OD); + + clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DSI0_ENGINE | + CG_CON1_DSI0_DIGITAL); +} + +void mtk_ddp_init(void) +{ + disp_clock_on(); +} + +void mtk_ddp_mode_set(const struct edid *edid) +{ + u32 fmt = OVL_INFMT_RGBA8888; + u32 bpp = edid->framebuffer_bits_per_pixel / 8; + + main_disp_path_setup(edid->mode.ha, edid->mode.va, + edid->mode.pixel_clock); + + rdma_start(); + + ovl_layer_config(fmt, bpp, edid->mode.ha, edid->mode.va); +} diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c new file mode 100644 index 0000000000..1d195719b0 --- /dev/null +++ b/src/soc/mediatek/mt8173/dsi.c @@ -0,0 +1,300 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, + const struct edid *edid) +{ + u32 txdiv0, txdiv1; + u64 pcw; + u32 reg; + u32 bit_per_pixel; + int i, data_rate; + + reg = read32(&mipi_tx0->dsi_bg_con); + + reg = (reg & (~RG_DSI_V02_SEL)) | (4 << 20); + reg = (reg & (~RG_DSI_V032_SEL)) | (4 << 17); + reg = (reg & (~RG_DSI_V04_SEL)) | (4 << 14); + reg = (reg & (~RG_DSI_V072_SEL)) | (4 << 11); + reg = (reg & (~RG_DSI_V10_SEL)) | (4 << 8); + reg = (reg & (~RG_DSI_V12_SEL)) | (4 << 5); + reg |= RG_DSI_BG_CKEN; + reg |= RG_DSI_BG_CORE_EN; + write32(&mipi_tx0->dsi_bg_con, reg); + udelay(30); + + clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, + 8 << 4 | RG_DSI_LNT_HS_BIAS_EN); + + setbits_le32(&mipi_tx0->dsi_con, + RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN); + + clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, + RG_DSI_MPPLL_SDM_PWR_ON); + + clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bit_per_pixel = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bit_per_pixel = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bit_per_pixel = 24; + break; + } + + /** + * data_rate = (pixel_clock / 1000) * bit_per_pixel * mipi_ratio / lane_num + * pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000. + * mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi. + * we set mipi_ratio is 1.02. + * lane_num + */ + data_rate = edid->mode.pixel_clock * 102 * bit_per_pixel / + (lanes * 1000 * 100); + if (data_rate > 500) { + txdiv0 = 0; + txdiv1 = 0; + } else if (data_rate >= 250) { + txdiv0 = 1; + txdiv1 = 0; + } else if (data_rate >= 125) { + txdiv0 = 2; + txdiv1 = 0; + } else if (data_rate >= 62) { + txdiv0 = 2; + txdiv1 = 1; + } else if (data_rate >= 50) { + txdiv0 = 2; + txdiv1 = 2; + } else { + printk(BIOS_ERR, "data rate (%u) must be >=50. Please check " + "pixel clock (%u), bpp (%u), and number of lanes (%u)\n", + data_rate, edid->mode.pixel_clock, bit_per_pixel, lanes); + return -1; + } + + clrsetbits_le32(&mipi_tx0->dsi_pll_con0, + RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 | + RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3); + + /** + * PLL PCW config + * PCW bit 24~30 = integer part of pcw + * PCW bit 0~23 = fractional part of pcw + * pcw = data_Rate*4*txdiv/(Ref_clk*2); + * Post DIV =4, so need data_Rate*4 + * Ref_clk is 26MHz + */ + pcw = (u64)(data_rate * (1 << txdiv0) * (1 << txdiv1)) << 24; + pcw /= 13; + write32(&mipi_tx0->dsi_pll_con2, pcw); + + setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); + + setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); + + for (i = 0; i < lanes; i++) + setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); + + setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + + udelay(40); + + clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); + clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); + + return data_rate; +} + +static void mtk_dsi_phy_timconfig(u32 data_rate) +{ + u32 timcon0, timcon1, timcon2, timcon3; + u32 cycle_time, ui, lpx; + + ui = 1000 / data_rate + 0x01; + cycle_time = 8000 / data_rate + 0x01; + lpx = 5; + + timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx; + timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 | + (4 * lpx); + timcon2 = ((div_round_up(0x64, cycle_time) + 0xa) << 24) | + (div_round_up(0x150, cycle_time) << 16); + timcon3 = (2 * lpx) << 16 | + div_round_up(80 + 52 * ui, cycle_time) << 8 | + div_round_up(0x40, cycle_time); + + write32(&dsi0->dsi_phy_timecon0, timcon0); + write32(&dsi0->dsi_phy_timecon1, timcon1); + write32(&dsi0->dsi_phy_timecon2, timcon2); + write32(&dsi0->dsi_phy_timecon3, timcon3); +} + +static void mtk_dsi_reset(void) +{ + setbits_le32(&dsi0->dsi_con_ctrl, 3); + clrbits_le32(&dsi0->dsi_con_ctrl, 1); +} + +static void mtk_dsi_clk_hs_mode_enable(void) +{ + setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); +} + +static void mtk_dsi_clk_hs_mode_disable(void) +{ + clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); +} + +static void mtk_dsi_set_mode(u32 mode_flags) +{ + u32 tmp_reg1 = 0; + + if (mode_flags & MIPI_DSI_MODE_VIDEO) { + tmp_reg1 = SYNC_PULSE_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + tmp_reg1 = BURST_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + tmp_reg1 = SYNC_PULSE_MODE; + } + + write32(&dsi0->dsi_mode_ctrl, tmp_reg1); +} + +static void mtk_dsi_rxtx_control(u32 lanes) +{ + u32 tmp_reg = 0; + + switch (lanes) { + case 1: + tmp_reg = 1 << 2; + break; + case 2: + tmp_reg = 3 << 2; + break; + case 3: + tmp_reg = 7 << 2; + break; + case 4: + default: + tmp_reg = 0xf << 2; + break; + } + + write32(&dsi0->dsi_txrx_ctrl, tmp_reg); +} + +static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, + const struct edid *edid) +{ + u32 hsync_active_byte; + u32 hbp_byte; + u32 hfp_byte; + u32 vbp_byte; + u32 vfp_byte; + u32 bpp; + u32 packet_fmt; + + if (format == MIPI_DSI_FMT_RGB565) + bpp = 2; + else + bpp = 3; + + vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - + edid->mode.vborder; + vfp_byte = edid->mode.vso - edid->mode.vborder; + + write32(&dsi0->dsi_vsa_nl, edid->mode.vspw); + write32(&dsi0->dsi_vbp_nl, vbp_byte); + write32(&dsi0->dsi_vfp_nl, vfp_byte); + write32(&dsi0->dsi_vact_nl, edid->mode.va); + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - + edid->mode.hborder) * bpp - 10; + else + hbp_byte = (edid->mode.hbl - edid->mode.hso - + edid->mode.hborder) * bpp - 10; + + hsync_active_byte = edid->mode.hspw * bpp - 10; + hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp - 12; + + write32(&dsi0->dsi_hsa_wc, hsync_active_byte); + write32(&dsi0->dsi_hbp_wc, hbp_byte); + write32(&dsi0->dsi_hfp_wc, hfp_byte); + + switch (format) { + case MIPI_DSI_FMT_RGB888: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + case MIPI_DSI_FMT_RGB666: + packet_fmt = LOOSELY_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + packet_fmt = PACKED_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB565: + packet_fmt = PACKED_PS_16BIT_RGB565; + break; + default: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + } + + packet_fmt |= edid->mode.ha * bpp & DSI_PS_WC; + write32(&dsi0->dsi_psctrl, packet_fmt); +} + +static void mtk_dsi_start(void) +{ + write32(&dsi0->dsi_start, 0); + write32(&dsi0->dsi_start, 1); +} + +int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, + const struct edid *edid) +{ + int data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid); + + if (data_rate < 0) + return -1; + + mtk_dsi_reset(); + mtk_dsi_phy_timconfig(data_rate); + mtk_dsi_rxtx_control(lanes); + mtk_dsi_clk_hs_mode_disable(); + mtk_dsi_config_vdo_timing(mode_flags, format, edid); + mtk_dsi_set_mode(mode_flags); + mtk_dsi_clk_hs_mode_enable(); + mtk_dsi_start(); + + return 0; +} diff --git a/src/soc/mediatek/mt8173/include/soc/addressmap.h b/src/soc/mediatek/mt8173/include/soc/addressmap.h index 398975679e..00c9a6e49c 100644 --- a/src/soc/mediatek/mt8173/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8173/include/soc/addressmap.h @@ -44,6 +44,8 @@ enum { APMIXED_BASE = IO_PHYS + 0x209000, CHA_DRAMCNAO_BASE = IO_PHYS + 0x20E000, CHB_DRAMCNAO_BASE = IO_PHYS + 0x213000, + MIPI_TX0_BASE = IO_PHYS + 0x215000, + MIPI_TX1_BASE = IO_PHYS + 0x216000, ANA_MIPI_CS1_BASE = IO_PHYS + 0x218000, UART0_BASE = IO_PHYS + 0x1002000, SPI_BASE = IO_PHYS + 0x100A000, @@ -53,6 +55,19 @@ enum { SSUSB_MAC_BASE = IO_PHYS + 0x1270000, SSUSB_IPPC_BASE = IO_PHYS + 0x1280700, SSUSB_SIF_BASE = IO_PHYS + 0x1290800, + MMSYS_BASE = IO_PHYS + 0x4000000, + DIS_OVL0_BASE = IO_PHYS + 0x400C000, + DIS_OVL1_BASE = IO_PHYS + 0x400D000, + DISP_RDMA0_BASE = IO_PHYS + 0x400E000, + DISP_RDMA1_BASE = IO_PHYS + 0x400F000, + DISP_RDMA2_BASE = IO_PHYS + 0x4010000, + DISP_COLOR0_BASE = IO_PHYS + 0x4013000, + DISP_COLOR1_BASE = IO_PHYS + 0x4014000, + DISP_UFOE_BASE = IO_PHYS + 0x401A000, + DSI0_BASE = IO_PHYS + 0x401B000, + DSI1_BASE = IO_PHYS + 0x401C000, + DISP_MUTEX_BASE = IO_PHYS + 0x4020000, + DISP_OD_BASE = IO_PHYS + 0x4023000, }; #endif /* __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H___ */ diff --git a/src/soc/mediatek/mt8173/include/soc/ddp.h b/src/soc/mediatek/mt8173/include/soc/ddp.h new file mode 100644 index 0000000000..9846b1ad40 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/ddp.h @@ -0,0 +1,432 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DDP_REG_H_ +#define _DDP_REG_H_ + +#include +#include + +struct mmsys_cfg_regs { + u32 mmsys_inten; + u32 mmsys_intsta; + u32 mjc_apb_tx_con; + u32 pwm_apb_err_addr; + u8 reserved0[12]; + u32 isp_mout_en; + u32 mdp_rdma0_mout_en; + u32 mdp_prz0_mout_en; + u32 mdp_prz1_mout_en; + u32 mdp_prz2_mout_en; + u32 mdp_tdshp0_mout_en; + u32 mdp_tdshp1_mout_en; + u32 mdp0_mout_en; + u32 mdp1_mout_en; + u32 disp_ovl0_mout_en; + u32 disp_ovl1_mout_en; + u32 disp_od_mout_en; + u32 disp_gamma_mout_en; + u32 disp_ufoe_mout_en; + u32 mmsys_mout_rst; + u32 mdp_prz0_sel_in; + u32 mdp_prz1_sel_in; + u32 mdp_prz2_sel_in; + u32 mdp_tdshp0_sel_in; + u32 mdp_tdshp1_sel_in; + u32 mdp0_sel_in; + u32 mdp1_sel_in; + u32 mdp_crop_sel_in; + u32 mdp_wdma_sel_in; + u32 mdp_wrot0_sel_in; + u32 mdp_wrot1_sel_in; + u32 disp_color0_sel_in; + u32 disp_color1_sel_in; + u32 disp_aal_sel_in; + u32 disp_path0_sel_in; + u32 disp_path1_sel_in; + u32 disp_wdma0_sel_in; + u32 disp_wdma1_sel_in; + u32 disp_ufoe_sel_in; + u32 dsi0_sel_in; + u32 dsi1_sel_in; + u32 dpi_sel_in; + u32 disp_rdma0_sout_sel_in; + u32 disp_rdma1_sout_sel_in; + u32 disp_rdma2_sout_sel_in; + u32 disp_color0_sout_sel_in; + u32 disp_color1_sout_sel_in; + u32 disp_path0_sout_sel_in; + u32 disp_path1_sout_sel_in; + u8 reserved1[36]; + u32 mmsys_misc; + u8 reserved2[12]; + u32 mmsys_cg_con0; + u32 mmsys_cg_set0; + u32 mmsys_cg_clr0; + u8 reserved3[4]; + u32 mmsys_cg_con1; + u32 mmsys_cg_set1; + u32 mmsys_cg_clr1; + u8 reserved4[4]; + u32 mmsys_hw_dcm_dis0; + u32 mmsys_hw_dcm_dis_set0; + u32 mmsys_hw_dcm_dis_clr0; + u8 reserved5[4]; + u32 mmsys_hw_dcm_dis1; + u32 mmsys_hw_dcm_dis_set1; + u32 mmsys_hw_dcm_dis_clr1; + u8 reserved6[4]; + u32 mmsys_sw0_rst_b; + u32 mmsys_sw1_rst_b; + u8 reserved7[8]; + u32 mmsys_lcm_rst_b; + u8 reserved8[20]; + u32 smi_n21mux_cfg_wr; + u32 smi_n21mux_cfg_rd; + u32 ela2gmc_base_addr; + u32 ela2gmc_base_addr_end; + u32 ela2gmc_final_addr; + u32 ela2gmc_status; + u8 reserved9[128]; + u32 disp_fake_eng_en; + u32 disp_fake_eng_rst; + u32 disp_fake_eng_con0; + u32 disp_fake_eng_con1; + u32 disp_fake_eng_rd_addr; + u32 disp_fake_eng_wr_addr; + u32 disp_fake_eng_state; + u8 reserved10[1508]; + u32 mmsys_mbist_con; + u32 mmsys_mbist_done; + u32 mmsys_mbist_holdb; + u32 mmsys_mbist_mode; + u32 mmsys_mbist_fail0; + u32 mmsys_mbist_fail1; + u32 mmsys_mbist_fail2; + u8 reserved11[4]; + u32 mmsys_mbist_bsel[4]; + u32 mmsys_mem_delsel[6]; + u8 reserved12[56]; + u32 mmsys_debug_out_sel; + u8 reserved13[12]; + u32 mmsys_dummy; + u8 reserved14[12]; + u32 mmsys_mbist_rp_rst_b; + u32 mmsys_mbist_rp_fail; + u32 mmsys_mbist_rp_ok; + u8 reserved15[4]; + u32 disp_dl_valid_0; + u32 disp_dl_valid_1; + u32 disp_dl_ready_0; + u32 disp_dl_ready_1; + u32 mdp_dl_valid_0; + u32 mdp_dl_valid_1; + u32 mdp_dl_ready_0; + u32 mdp_dl_ready_1; + u32 smi_larb0_greq; + u8 reserved16[48]; + u32 hdmi_en; +}; + +check_member(mmsys_cfg_regs, hdmi_en, 0x904); +static struct mmsys_cfg_regs * const mmsys_cfg = (void *) MMSYS_BASE; + +/* DISP_REG_CONFIG_MMSYS_CG_CON0 + Configures free-run clock gating 0 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON0_SMI_COMMON = BIT(0), + CG_CON0_SMI_LARB0 = BIT(1), + CG_CON0_CAM_MDP = BIT(2), + CG_CON0_MDP_RDMA0 = BIT(3), + CG_CON0_MDP_RDMA1 = BIT(4), + CG_CON0_MDP_RSZ0 = BIT(5), + CG_CON0_MDP_RSZ1 = BIT(6), + CG_CON0_MDP_RSZ2 = BIT(7), + CG_CON0_MDP_TDSHP0 = BIT(8), + CG_CON0_MDP_TDSHP1 = BIT(9), + CG_CON0_MDP_CROP = BIT(10), + CG_CON0_MDP_WDMA = BIT(11), + CG_CON0_MDP_WROT0 = BIT(12), + CG_CON0_MDP_WROT1 = BIT(13), + CG_CON0_FAKE_ENG = BIT(14), + CG_CON0_MUTEX_32K = BIT(15), + CG_CON0_DISP_OVL0 = BIT(16), + CG_CON0_DISP_OVL1 = BIT(17), + CG_CON0_DISP_RDMA0 = BIT(18), + CG_CON0_DISP_RDMA1 = BIT(19), + CG_CON0_DISP_RDMA2 = BIT(20), + CG_CON0_DISP_WDMA0 = BIT(21), + CG_CON0_DISP_WDMA1 = BIT(22), + CG_CON0_DISP_COLOR0 = BIT(23), + CG_CON0_DISP_COLOR1 = BIT(24), + CG_CON0_DISP_AAL = BIT(25), + CG_CON0_DISP_GAMMA = BIT(26), + CG_CON0_DISP_UFOE = BIT(27), + CG_CON0_DISP_SPLIT0 = BIT(28), + CG_CON0_DISP_SPLIT1 = BIT(29), + CG_CON0_DISP_MERGE = BIT(30), + CG_CON0_DISP_OD = BIT(31), + CG_CON0_ALL = 0xffffffff +}; + +/* DISP_REG_CONFIG_MMSYS_CG_CON1 + Configures free-run clock gating 1 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON1_DISP_PWM0_MM = BIT(0), + CG_CON1_DISP_PWM0_26M = BIT(1), + CG_CON1_DISP_PWM1_MM = BIT(2), + CG_CON1_DISP_PWM1_26M = BIT(3), + CG_CON1_DSI0_ENGINE = BIT(4), + CG_CON1_DSI0_DIGITAL = BIT(5), + CG_CON1_DSI1_ENGINE = BIT(6), + CG_CON1_DSI1_DIGITAL = BIT(7), + CG_CON1_DPI_PIXEL = BIT(8), + CG_CON1_DPI_ENGINE = BIT(9), + + CG_CON1_ALL = 0xffffffff +}; + +enum { + OVL0_MOUT_EN_COLOR0 = BIT(0), + OD_MOUT_EN_RDMA0 = BIT(0), + UFOE_MOUT_EN_DSI0 = BIT(0), + COLOR0_SEL_IN_OVL0 = BIT(0), +}; + +struct disp_mutex_regs { + u32 inten; + u32 intsta; + u8 reserved0[24]; + struct { + u32 en; + u32 dummy; + u32 rst; + u32 mod; + u32 sof; + u32 reserved[3]; + } mutex[6]; + u8 reserved1[32]; + u32 debug_out_sel; +}; + +check_member(disp_mutex_regs, debug_out_sel, 0x100); +static struct disp_mutex_regs * const disp_mutex = (void *) DISP_MUTEX_BASE; + +enum { + MUTEX_MOD_DISP_OVL0 = BIT(11), + MUTEX_MOD_DISP_RDMA0 = BIT(13), + MUTEX_MOD_DISP_COLOR0 = BIT(18), + MUTEX_MOD_DISP_AAL = BIT(20), + MUTEX_MOD_DISP_UFOE = BIT(22), + MUTEX_MOD_DISP_OD = BIT(25), + MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | MUTEX_MOD_DISP_RDMA0 | + MUTEX_MOD_DISP_COLOR0 | MUTEX_MOD_DISP_AAL | + MUTEX_MOD_DISP_UFOE | MUTEX_MOD_DISP_OD, +}; + +struct disp_ovl_regs { + u32 sta; + u32 inten; + u32 intsta; + u32 en; + u32 trig; + u32 rst; + u8 reserved0[8]; + u32 roi_size; + u32 datapath_con; + u32 roi_bgclr; + u32 src_con; + struct { + u32 con; + u32 srckey; + u32 src_size; + u32 offset; + u32 reserved0; + u32 pitch; + u32 reserved1[2]; + } layer[4]; + u8 reserved8[16]; + struct { + u32 ctrl; + u32 mem_start_trig; + u32 mem_gmc_setting; + u32 mem_slow_con; + u32 fifo_ctrl; + u8 reserved[12]; + } rdma[4]; + u8 reserved12[148]; + u32 debug_mon_sel; + u8 reserved13[8]; + u32 rdma_mem_gmc_setting2[4]; + u8 reserved14[16]; + u32 dummy; + u8 reserved15[60]; + u32 flow_ctrl_dbg; + u32 addcon_dbg; + u32 outmux_dbg; + u32 rdma_dbg[4]; + u8 reserved16[3300]; + u32 l0_addr; + u8 reserved17[28]; + u32 l1_addr; + u8 reserved18[28]; + u32 l2_addr; + u8 reserved19[28]; + u32 l3_addr; +}; + +check_member(disp_ovl_regs, l3_addr, 0xFA0); +static struct disp_ovl_regs * const disp_ovl[2] = + {(void *) DIS_OVL0_BASE, (void *) DIS_OVL1_BASE}; + +struct disp_rdma_regs { + u32 int_enable; + u32 int_status; + u8 reserved0[8]; + u32 global_con; + u32 size_con_0; + u32 size_con_1; + u32 target_line; + u8 reserved1[4]; + u32 mem_con; + u32 mem_start_addr; + u32 mem_src_pitch; + u32 mem_gmc_setting_0; + u32 mem_slow_con; + u32 mem_gmc_setting_1; + u8 reserved2[4]; + u32 fifo_con; + u8 reserved3[16]; + u32 cf[3][3]; + u32 cf_pre_add[3]; + u32 cf_post_add[3]; + u32 dummy; + u32 debug_out_sel; +}; + +enum { + RDMA_ENGINE_EN = BIT(0), + RDMA_FIFO_UNDERFLOW_EN = BIT(31), + RDMA_MEM_GMC = 0x40402020, +}; + +check_member(disp_rdma_regs, debug_out_sel, 0x94); +static struct disp_rdma_regs * const disp_rdma[3] = + {(void *)DISP_RDMA0_BASE, (void *)DISP_RDMA1_BASE, (void *)DISP_RDMA2_BASE}; + +struct disp_od_regs { + u32 en; + u32 reset; + u32 inten; + u32 ints; + u32 status; + u8 reserved0[12]; + u32 cfg; + u32 input_count; + u32 output_count; + u32 chks_um; + u32 size; + u8 reserved1[12]; + u32 hsync_width; + u32 vsync_width; + u32 misc; +}; + +check_member(disp_od_regs, misc, 0x48); +static struct disp_od_regs * const disp_od = (void *)DISP_OD_BASE; + +enum { + OD_RELAY_MODE = BIT(0), +}; + +struct disp_ufoe_regs { + u32 start; + u32 inten; + u32 intsta; + u32 dbuf; + u8 reserved0[4]; + u32 crc; + u32 sw_scratch; + u8 reserved1[4]; + u32 cr0p6_pad; + u8 reserved2[4]; + u32 ck_on; + u8 reserved3[36]; + u32 frame_width; + u32 frame_height; + u32 outen; + u8 reserved4[148]; + u32 r0_crc; + u8 reserved5[12]; + u32 cfg[5]; + u8 reserved6[12]; + u32 ro[5]; + u8 reserved7[12]; + u32 dbg[8]; +}; + +check_member(disp_ufoe_regs, dbg[7], 0x15C); +static struct disp_ufoe_regs * const disp_ufoe = (void *)DISP_UFOE_BASE; + +enum { + UFO_BYPASS = BIT(2), +}; + +struct disp_color_regs { + u8 reserved0[1024]; + u32 cfg_main; + u8 reserved1[2044]; + u32 start; + u8 reserved2[76]; + u32 width; + u32 height; +}; + +check_member(disp_color_regs, cfg_main, 0x400); +check_member(disp_color_regs, start, 0xC00); +check_member(disp_color_regs, width, 0xC50); +check_member(disp_color_regs, height, 0xC54); +static struct disp_color_regs * const disp_color[2] = + {(void *)DISP_COLOR0_BASE, (void *)DISP_COLOR1_BASE}; + +enum { + COLOR_BYPASS_ALL = BIT(7), + COLOR_SEQ_SEL = BIT(13), +}; + +enum OVL_INPUT_FORMAT { + OVL_INFMT_RGB565 = 0, + OVL_INFMT_RGB888 = 1, + OVL_INFMT_RGBA8888 = 2, + OVL_INFMT_ARGB8888 = 3, + OVL_INFMT_UYVY = 4, + OVL_INFMT_YUYV = 5, + OVL_INFMT_UNKNOWN = 16, + + OVL_COLOR_BASE = 30, + OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE, + OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE, + OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE, + OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE, +}; + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); + +#endif diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h new file mode 100644 index 0000000000..1abbd78ae9 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DSI_REG_H_ +#define _DSI_REG_H_ + +#include +#include + +enum mipi_dsi_pixel_format { + MIPI_DSI_FMT_RGB888, + MIPI_DSI_FMT_RGB666, + MIPI_DSI_FMT_RGB666_PACKED, + MIPI_DSI_FMT_RGB565 +}; + +/* video mode */ +enum { + MIPI_DSI_MODE_VIDEO = BIT(0), + /* video burst mode */ + MIPI_DSI_MODE_VIDEO_BURST = BIT(1), + /* video pulse mode */ + MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2), + /* enable auto vertical count mode */ + MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3), + /* enable hsync-end packets in vsync-pulse and v-porch area */ + MIPI_DSI_MODE_VIDEO_HSE = BIT(4), + /* disable hfront-porch area */ + MIPI_DSI_MODE_VIDEO_HFP = BIT(5), + /* disable hback-porch area */ + MIPI_DSI_MODE_VIDEO_HBP = BIT(6), + /* disable hsync-active area */ + MIPI_DSI_MODE_VIDEO_HSA = BIT(7), + /* flush display FIFO on vsync pulse */ + MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8), + /* disable EoT packets in HS mode */ + MIPI_DSI_MODE_EOT_PACKET = BIT(9), + /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ + MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10), + /* transmit data in low power */ + MIPI_DSI_MODE_LPM = BIT(11) +}; + +struct dsi_regs { + u32 dsi_start; + u8 reserved0[4]; + u32 dsi_inten; + u32 dsi_intsta; + u32 dsi_con_ctrl; + u32 dsi_mode_ctrl; + u32 dsi_txrx_ctrl; + u32 dsi_psctrl; + u32 dsi_vsa_nl; + u32 dsi_vbp_nl; + u32 dsi_vfp_nl; + u32 dsi_vact_nl; + u8 reserved1[32]; + u32 dsi_hsa_wc; + u32 dsi_hbp_wc; + u32 dsi_hfp_wc; + u32 dsi_bllp_wc; + u8 reserved2[4]; + u32 dsi_hstx_cklp_wc; + u8 reserved3[156]; + u32 dsi_phy_lccon; + u32 dsi_phy_ld0con; + u8 reserved4[4]; + u32 dsi_phy_timecon0; + u32 dsi_phy_timecon1; + u32 dsi_phy_timecon2; + u32 dsi_phy_timecon3; +}; + +check_member(dsi_regs, dsi_phy_lccon, 0x104); +check_member(dsi_regs, dsi_phy_timecon3, 0x11c); +static struct dsi_regs * const dsi0 = (void *)DSI0_BASE; + +/* DSI_MODE_CTRL */ +enum { + MODE = 3, + CMD_MODE = 0, + SYNC_PULSE_MODE = 1, + SYNC_EVENT_MODE = 2, + BURST_MODE = 3, + FRM_MODE = BIT(16), + MIX_MODE = BIT(17) +}; + +/* DSI_PSCTRL */ +enum { + DSI_PS_WC = 0x3fff, + DSI_PS_SEL = (3 << 16), + PACKED_PS_16BIT_RGB565 = (0 << 16), + LOOSELY_PS_18BIT_RGB666 = (1 << 16), + PACKED_PS_18BIT_RGB666 = (2 << 16), + PACKED_PS_24BIT_RGB888 = (3 << 16) +}; + +/* DSI_PHY_LCCON */ +enum { + LC_HS_TX_EN = BIT(0), + LC_ULPM_EN = BIT(1), + LC_WAKEUP_EN = BIT(2) +}; + +/*DSI_PHY_LD0CON */ +enum { + LD0_RM_TRIG_EN = BIT(0), + LD0_ULPM_EN = BIT(1), + LD0_WAKEUP_EN = BIT(2) +}; + +enum { + LPX = (0xff << 0), + HS_PRPR = (0xff << 8), + HS_ZERO = (0xff << 16), + HS_TRAIL = (0xff << 24) +}; + +enum { + TA_GO = (0xff << 0), + TA_SURE = (0xff << 8), + TA_GET = (0xff << 16), + DA_HS_EXIT = (0xff << 24) +}; + +enum { + CONT_DET = (0xff << 0), + CLK_ZERO = (0xf << 16), + CLK_TRAIL = (0xff << 24) +}; + +enum { + CLK_HS_PRPR = (0xff << 0), + CLK_HS_POST = (0xff << 8), + CLK_HS_EXIT = (0xf << 16) +}; + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 dsi_con; + u32 dsi_clock_lane; + u32 dsi_data_lane[4]; + u8 reserved0[40]; + u32 dsi_top_con; + u32 dsi_bg_con; + u8 reserved1[8]; + u32 dsi_pll_con0; + u32 dsi_pll_con1; + u32 dsi_pll_con2; + u32 dsi_pll_con3; + u32 dsi_pll_chg; + u32 dsi_pll_top; + u32 dsi_pll_pwr; + u8 reserved2[4]; + u32 dsi_rgs; + u32 dsi_gpi_en; + u32 dsi_gpi_pull; + u32 dsi_phy_sel; + u32 dsi_sw_ctrl_en; + u32 dsi_sw_ctrl_con0; + u32 dsi_sw_ctrl_con1; + u32 dsi_sw_ctrl_con2; + u32 dsi_dbg_con; + u32 dsi_dbg_out; + u32 dsi_apb_async_sta; +}; + +check_member(mipi_tx_regs, dsi_top_con, 0x40); +check_member(mipi_tx_regs, dsi_pll_pwr, 0x68); + +static struct mipi_tx_regs * const mipi_tx0 = (void *)MIPI_TX0_BASE; + +/* MIPITX_DSI0_CON */ +enum { + RG_DSI0_LDOCORE_EN = BIT(0), + RG_DSI0_CKG_LDOOUT_EN = BIT(1), + RG_DSI0_BCLK_SEL = (3 << 2), + RG_DSI0_LD_IDX_SEL = (7 << 4), + RG_DSI0_PHYCLK_SEL = (2 << 8), + RG_DSI0_DSICLK_FREQ_SEL = BIT(10), + RG_DSI0_LPTX_CLMP_EN = BIT(11) +}; + +/* MIPITX_DSI0_CLOCK_LANE */ +enum { + LDOOUT_EN = BIT(0), + CKLANE_EN = BIT(1), + IPLUS1 = BIT(2), + LPTX_IPLUS2 = BIT(3), + LPTX_IMINUS = BIT(4), + LPCD_IPLUS = BIT(5), + LPCD_IMLUS = BIT(6), + RT_CODE = (0xf << 8) +}; + +/* MIPITX_DSI_TOP_CON */ +enum { + RG_DSI_LNT_INTR_EN = BIT(0), + RG_DSI_LNT_HS_BIAS_EN = BIT(1), + RG_DSI_LNT_IMP_CAL_EN = BIT(2), + RG_DSI_LNT_TESTMODE_EN = BIT(3), + RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4), + RG_DSI_LNT_AIO_SEL = (7 << 8), + RG_DSI_PAD_TIE_LOW_EN = BIT(11), + RG_DSI_DEBUG_INPUT_EN = BIT(12), + RG_DSI_PRESERVE = (7 << 13) +}; + +/* MIPITX_DSI_BG_CON */ +enum { + RG_DSI_BG_CORE_EN = BIT(0), + RG_DSI_BG_CKEN = BIT(1), + RG_DSI_BG_DIV = (0x3 << 2), + RG_DSI_BG_FAST_CHARGE = BIT(4), + RG_DSI_V12_SEL = (7 << 5), + RG_DSI_V10_SEL = (7 << 8), + RG_DSI_V072_SEL = (7 << 11), + RG_DSI_V04_SEL = (7 << 14), + RG_DSI_V032_SEL = (7 << 17), + RG_DSI_V02_SEL = (7 << 20), + rsv_23 = BIT(23), + RG_DSI_BG_R1_TRIM = (0xf << 24), + RG_DSI_BG_R2_TRIM = (0xf << 28) +}; + +/* MIPITX_DSI_PLL_CON0 */ +enum { + RG_DSI0_MPPLL_PLL_EN = BIT(0), + RG_DSI0_MPPLL_PREDIV = (3 << 1), + RG_DSI0_MPPLL_TXDIV0 = (3 << 3), + RG_DSI0_MPPLL_TXDIV1 = (3 << 5), + RG_DSI0_MPPLL_POSDIV = (7 << 7), + RG_DSI0_MPPLL_MONVC_EN = BIT(10), + RG_DSI0_MPPLL_MONREF_EN = BIT(11), + RG_DSI0_MPPLL_VOD_EN = BIT(12) +}; + +/* MIPITX_DSI_PLL_CON1 */ +enum { + RG_DSI0_MPPLL_SDM_FRA_EN = BIT(0), + RG_DSI0_MPPLL_SDM_SSC_PH_INIT = BIT(1), + RG_DSI0_MPPLL_SDM_SSC_EN = BIT(2), + RG_DSI0_MPPLL_SDM_SSC_PRD = (0xffff << 16) +}; + +/* MIPITX_DSI_PLL_PWR */ +enum { + RG_DSI_MPPLL_SDM_PWR_ON = BIT(0), + RG_DSI_MPPLL_SDM_ISO_EN = BIT(1), + RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8) +}; + +int mtk_dsi_init(u32 mode_flags, enum mipi_dsi_pixel_format format, u32 lanes, + const struct edid *edid); + +#endif -- cgit v1.2.3