From 46ef53621265feeeebca475a0078f6bd301fcb35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 15 Sep 2021 16:35:56 +0200 Subject: soc/intel/icelake: correct wrong gpio SMI register base offsets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reference: Intel doc# 341081-002. Change-Id: If6e0503cc042c26c4077b8b32bb447d4e3a9bb6a Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57675 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/soc/intel/icelake/include/soc/gpio_defs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index b9238a5d2b..1291304384 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -253,8 +253,8 @@ #define HOSTSW_OWN_REG_0 0xb0 #define GPI_INT_STS_0 0x100 #define GPI_INT_EN_0 0x110 -#define GPI_SMI_STS_0 0x180 -#define GPI_SMI_EN_0 0x1A0 +#define GPI_SMI_STS_0 0x170 +#define GPI_SMI_EN_0 0x190 #define GPI_NMI_STS_0 0x1b0 #define GPI_NMI_EN_0 0x1d0 #define PAD_CFG_BASE 0x600 -- cgit v1.2.3