From 466edb51b4b0c19486f14f43bee8d6834c52abc9 Mon Sep 17 00:00:00 2001
From: Raul E Rangel <rrangel@chromium.org>
Date: Tue, 9 Feb 2021 11:24:13 -0700
Subject: soc/amd/common/blocks/lpc: Remove common SPI registers

Use the SoC versions instead.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 src/soc/amd/common/block/include/amdblocks/lpc.h | 9 ---------
 src/soc/amd/common/block/lpc/lpc.c               | 3 ++-
 src/soc/amd/common/block/lpc/lpc_util.c          | 1 +
 src/soc/amd/common/block/spi/fch_spi.c           | 1 +
 src/soc/amd/stoneyridge/southbridge.c            | 1 +
 5 files changed, 5 insertions(+), 10 deletions(-)

(limited to 'src/soc')

diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index fbedb71374..4e2660b8a0 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -113,15 +113,6 @@
 
 #define LPC_WIDEIO2_GENERIC_PORT	0x90
 
-#define SPIROM_BASE_ADDRESS_REGISTER	0xa0
-#define SPI_BASE_ALIGNMENT		BIT(6)
-#define   SPI_BASE_RESERVED		(BIT(4) | BIT(5))
-#define   ROUTE_TPM_2_SPI		BIT(3)
-#define   SPI_ABORT_ENABLE		BIT(2)
-#define   SPI_ROM_ENABLE		BIT(1)
-#define   SPI_ROM_ALT_ENABLE		BIT(0)
-#define   SPI_PRESERVE_BITS		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
-
 /* LPC register 0xb8 is DWORD, here there are definitions for byte
    access. For example, bits 31-24 are accessed through byte access
    at register 0xbb. */
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 7f3bea0da7..d68814ba9f 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -16,8 +16,9 @@
 #include <amdblocks/espi.h>
 #include <amdblocks/lpc.h>
 #include <soc/acpi.h>
-#include <soc/southbridge.h>
 #include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/southbridge.h>
 
 /* Most systems should have already enabled the bridge */
 void __weak soc_late_lpc_bridge_enable(void) { }
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index eb129dc00d..fb231dd7e9 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -8,6 +8,7 @@
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/lpc.h>
 #include <soc/iomap.h>
+#include <soc/lpc.h>
 #include <soc/southbridge.h>
 
 /* The LPC-ISA bridge is always at D14F3 */
diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c
index c39147a8b3..a644d273a1 100644
--- a/src/soc/amd/common/block/spi/fch_spi.c
+++ b/src/soc/amd/common/block/spi/fch_spi.c
@@ -6,6 +6,7 @@
 #include <arch/mmio.h>
 #include <console/console.h>
 #include <soc/iomap.h>
+#include <soc/lpc.h>
 #include <stdint.h>
 
 static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm)
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index c53bcf05a5..f8a705ed83 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -26,6 +26,7 @@
 #include <soc/pci_devs.h>
 #include <agesa_headers.h>
 #include <soc/acpi.h>
+#include <soc/lpc.h>
 #include <soc/nvs.h>
 #include <types.h>
 
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